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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:53 2011
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//-- Invoked Fri Mar 25 23:36:53 2011
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//--
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//--
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//-- Source file: dma_reg.v
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//-- Source file: dma_reg.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_reg(clk,reset,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,core0_idle,ch_int_all_proc0,int_all_proc,core0_clkdiv,core0_ch_start,joint_mode0,rd_prio_top0,rd_prio_high0,rd_prio_top_num0,rd_prio_high_num0,wr_prio_top0,wr_prio_high0,wr_prio_top_num0,wr_prio_high_num0,periph_rx_req_reg,periph_tx_req_reg,periph_rx_clr,periph_tx_clr);
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module dma_axi64_reg(clk,reset,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,core0_idle,ch_int_all_proc0,int_all_proc,core0_clkdiv,core0_ch_start,joint_mode0,rd_prio_top0,rd_prio_high0,rd_prio_top_num0,rd_prio_high_num0,wr_prio_top0,wr_prio_high0,wr_prio_top_num0,wr_prio_high_num0,periph_rx_req_reg,periph_tx_req_reg,periph_rx_clr,periph_tx_clr);
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input clk;
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input clk;
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input reset;
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input reset;
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input pclken;
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input pclken;
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input psel;
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input psel;
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input penable;
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input penable;
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input [7:0] paddr;
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input [7:0] paddr;
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input pwrite;
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input pwrite;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [31:0] prdata;
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output [31:0] prdata;
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output pslverr;
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output pslverr;
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input core0_idle;
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input core0_idle;
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input [8*1-1:0] ch_int_all_proc0;
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input [8*1-1:0] ch_int_all_proc0;
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output [1-1:0] int_all_proc;
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output [1-1:0] int_all_proc;
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output [3:0] core0_clkdiv;
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output [3:0] core0_clkdiv;
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output [7:0] core0_ch_start;
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output [7:0] core0_ch_start;
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output joint_mode0;
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output joint_mode0;
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output rd_prio_top0;
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output rd_prio_top0;
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output rd_prio_high0;
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output rd_prio_high0;
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output [2:0] rd_prio_top_num0;
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output [2:0] rd_prio_top_num0;
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output [2:0] rd_prio_high_num0;
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output [2:0] rd_prio_high_num0;
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output wr_prio_top0;
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output wr_prio_top0;
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output wr_prio_high0;
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output wr_prio_high0;
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output [2:0] wr_prio_top_num0;
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output [2:0] wr_prio_top_num0;
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output [2:0] wr_prio_high_num0;
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output [2:0] wr_prio_high_num0;
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output [31:1] periph_rx_req_reg;
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output [31:1] periph_rx_req_reg;
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output [31:1] periph_tx_req_reg;
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output [31:1] periph_tx_req_reg;
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input [31:1] periph_rx_clr;
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input [31:1] periph_rx_clr;
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input [31:1] periph_tx_clr;
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input [31:1] periph_tx_clr;
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`include "dma_axi64_reg_params.v"
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`include "dma_axi64_reg_params.v"
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wire [31:0] user_def_stat;
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wire [31:0] user_def_stat;
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wire [31:0] user_def0_stat0;
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wire [31:0] user_def0_stat0;
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wire [31:0] user_def0_stat1;
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wire [31:0] user_def0_stat1;
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wire user_def_proj;
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wire user_def_proj;
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wire [3:0] user_def_proc_num;
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wire [3:0] user_def_proc_num;
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wire user_def_dual_core;
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wire user_def_dual_core;
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wire user_def_ic;
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wire user_def_ic;
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wire user_def_ic_dual_port;
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wire user_def_ic_dual_port;
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wire user_def_clkgate;
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wire user_def_clkgate;
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wire user_def_port0_mux;
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wire user_def_port0_mux;
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wire user_def_port1_mux;
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wire user_def_port1_mux;
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wire wr_joint0;
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wire wr_joint0;
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wire wr_clkdiv0;
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wire wr_clkdiv0;
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wire wr_start0;
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wire wr_start0;
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wire wr_prio0;
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wire wr_prio0;
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wire [7:0] proc0_int_stat0;
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wire [7:0] proc0_int_stat0;
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wire [15:0] proc0_int_stat;
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wire [15:0] proc0_int_stat;
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wire proc0_int;
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wire proc0_int;
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wire [1-1:0] int_all_proc_pre;
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wire [1-1:0] int_all_proc_pre;
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reg [1-1:0] int_all_proc;
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reg [1-1:0] int_all_proc;
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wire wr_periph_rx;
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wire wr_periph_rx;
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wire wr_periph_tx;
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wire wr_periph_tx;
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reg [31:1] periph_rx_req_reg;
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reg [31:1] periph_rx_req_reg;
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reg [31:1] periph_tx_req_reg;
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reg [31:1] periph_tx_req_reg;
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wire [7:0] gpaddr;
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wire [7:0] gpaddr;
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wire gpwrite;
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wire gpwrite;
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wire gpread;
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wire gpread;
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reg [31:0] prdata_pre;
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reg [31:0] prdata_pre;
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reg pslverr_pre;
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reg pslverr_pre;
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reg [31:0] prdata;
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reg [31:0] prdata;
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reg pslverr;
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reg pslverr;
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assign wr_joint0 = gpwrite & gpaddr == CORE0_JOINT;
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assign wr_joint0 = gpwrite & gpaddr == CORE0_JOINT;
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assign wr_clkdiv0 = gpwrite & gpaddr == CORE0_CLKDIV;
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assign wr_clkdiv0 = gpwrite & gpaddr == CORE0_CLKDIV;
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assign wr_start0 = gpwrite & gpaddr == CORE0_START;
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assign wr_start0 = gpwrite & gpaddr == CORE0_START;
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assign wr_prio0 = gpwrite & gpaddr == CORE0_PRIO;
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assign wr_prio0 = gpwrite & gpaddr == CORE0_PRIO;
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dma_axi64_reg_core0 dma_axi64_reg_core0(
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dma_axi64_reg_core0 dma_axi64_reg_core0(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.wr_joint(wr_joint0),
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.wr_joint(wr_joint0),
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.wr_clkdiv(wr_clkdiv0),
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.wr_clkdiv(wr_clkdiv0),
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.wr_start(wr_start0),
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.wr_start(wr_start0),
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.wr_prio(wr_prio0),
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.wr_prio(wr_prio0),
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.pwdata(pwdata),
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.pwdata(pwdata),
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.clkdiv(core0_clkdiv),
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.clkdiv(core0_clkdiv),
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.ch_start(core0_ch_start),
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.ch_start(core0_ch_start),
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.joint_mode(joint_mode0),
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.joint_mode(joint_mode0),
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.rd_prio_top(rd_prio_top0),
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.rd_prio_top(rd_prio_top0),
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.rd_prio_high(rd_prio_high0),
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.rd_prio_high(rd_prio_high0),
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.rd_prio_top_num(rd_prio_top_num0),
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.rd_prio_top_num(rd_prio_top_num0),
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.rd_prio_high_num(rd_prio_high_num0),
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.rd_prio_high_num(rd_prio_high_num0),
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.wr_prio_top(wr_prio_top0),
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.wr_prio_top(wr_prio_top0),
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.wr_prio_high(wr_prio_high0),
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.wr_prio_high(wr_prio_high0),
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.wr_prio_top_num(wr_prio_top_num0),
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.wr_prio_top_num(wr_prio_top_num0),
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.wr_prio_high_num(wr_prio_high_num0),
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.wr_prio_high_num(wr_prio_high_num0),
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.user_def_stat0(user_def0_stat0),
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.user_def_stat0(user_def0_stat0),
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.user_def_stat1(user_def0_stat1),
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.user_def_stat1(user_def0_stat1),
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.ch_int_all_proc(ch_int_all_proc0),
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.ch_int_all_proc(ch_int_all_proc0),
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.proc0_int_stat(proc0_int_stat0)
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.proc0_int_stat(proc0_int_stat0)
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);
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);
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assign user_def_proj = 0;
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assign user_def_proj = 0;
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assign user_def_proc_num = 1;
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assign user_def_proc_num = 1;
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assign user_def_dual_core = 0;
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assign user_def_dual_core = 0;
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assign user_def_ic = 0;
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assign user_def_ic = 0;
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assign user_def_ic_dual_port = 0;
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assign user_def_ic_dual_port = 0;
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assign user_def_clkgate = 0;
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assign user_def_clkgate = 0;
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assign user_def_port0_mux = 0;
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assign user_def_port0_mux = 0;
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assign user_def_port1_mux = 0;
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assign user_def_port1_mux = 0;
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assign user_def_stat =
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assign user_def_stat =
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{user_def_proj, //[31]
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{user_def_proj, //[31]
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{20{1'b0}}, //[30:11]
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{20{1'b0}}, //[30:11]
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user_def_port1_mux, //[10]
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user_def_port1_mux, //[10]
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user_def_port0_mux, //[9]
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user_def_port0_mux, //[9]
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user_def_clkgate, //[8]
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user_def_clkgate, //[8]
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user_def_ic_dual_port, //[7]
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user_def_ic_dual_port, //[7]
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user_def_ic, //[6]
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user_def_ic, //[6]
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user_def_dual_core, //[5]
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user_def_dual_core, //[5]
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1'b0, //[4]
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1'b0, //[4]
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user_def_proc_num //[3:0]
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user_def_proc_num //[3:0]
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};
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};
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assign gpaddr = {8{psel}} & paddr;
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assign gpaddr = {8{psel}} & paddr;
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assign gpwrite = psel & (~penable) & pwrite;
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assign gpwrite = psel & (~penable) & pwrite;
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assign gpread = psel & (~penable) & (~pwrite);
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assign gpread = psel & (~penable) & (~pwrite);
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assign wr_periph_rx = gpwrite & gpaddr == PERIPH_RX_CTRL;
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assign wr_periph_rx = gpwrite & gpaddr == PERIPH_RX_CTRL;
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assign wr_periph_tx = gpwrite & gpaddr == PERIPH_TX_CTRL;
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assign wr_periph_tx = gpwrite & gpaddr == PERIPH_TX_CTRL;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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periph_rx_req_reg <= #1 {31{1'b0}};
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periph_rx_req_reg <= #1 {31{1'b0}};
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else if (wr_periph_rx | (|periph_rx_clr))
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else if (wr_periph_rx | (|periph_rx_clr))
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periph_rx_req_reg <= #1 ({31{wr_periph_rx}} & pwdata[31:1]) & (~periph_rx_clr);
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periph_rx_req_reg <= #1 ({31{wr_periph_rx}} & pwdata[31:1]) & (~periph_rx_clr);
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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periph_tx_req_reg <= #1 {31{1'b0}};
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periph_tx_req_reg <= #1 {31{1'b0}};
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else if (wr_periph_tx | (|periph_tx_clr))
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else if (wr_periph_tx | (|periph_tx_clr))
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periph_tx_req_reg <= #1 ({31{wr_periph_tx}} & pwdata[31:1]) & (~periph_tx_clr);
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periph_tx_req_reg <= #1 ({31{wr_periph_tx}} & pwdata[31:1]) & (~periph_tx_clr);
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assign proc0_int_stat = {proc0_int_stat0};
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assign proc0_int_stat = {proc0_int_stat0};
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assign proc0_int = |proc0_int_stat;
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assign proc0_int = |proc0_int_stat;
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assign int_all_proc_pre = {proc0_int};
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assign int_all_proc_pre = {proc0_int};
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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int_all_proc <= #1 {1{1'b0}};
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int_all_proc <= #1 {1{1'b0}};
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else
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else
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int_all_proc <= #1 int_all_proc_pre;
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int_all_proc <= #1 int_all_proc_pre;
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always @(*)
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always @(*)
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begin
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begin
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prdata_pre = {32{1'b0}};
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prdata_pre = {32{1'b0}};
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case (gpaddr)
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case (gpaddr)
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PROC0_STATUS : prdata_pre = {{16{1'b0}}, proc0_int_stat0};
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PROC0_STATUS : prdata_pre = {{16{1'b0}}, proc0_int_stat0};
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CORE0_JOINT : prdata_pre = {{31{1'b0}}, joint_mode0};
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CORE0_JOINT : prdata_pre = {{31{1'b0}}, joint_mode0};
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CORE0_PRIO : prdata_pre = {{16{1'b0}}, wr_prio_high0, wr_prio_high_num0, wr_prio_top0, wr_prio_top_num0, rd_prio_high0, rd_prio_high_num0, rd_prio_top0, rd_prio_top_num0};
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CORE0_PRIO : prdata_pre = {{16{1'b0}}, wr_prio_high0, wr_prio_high_num0, wr_prio_top0, wr_prio_top_num0, rd_prio_high0, rd_prio_high_num0, rd_prio_top0, rd_prio_top_num0};
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CORE0_CLKDIV : prdata_pre = {{28{1'b0}}, core0_clkdiv};
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CORE0_CLKDIV : prdata_pre = {{28{1'b0}}, core0_clkdiv};
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CORE0_START : prdata_pre = {32{1'b0}};
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CORE0_START : prdata_pre = {32{1'b0}};
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PERIPH_RX_CTRL : prdata_pre = {periph_rx_req_reg, 1'b0};
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PERIPH_RX_CTRL : prdata_pre = {periph_rx_req_reg, 1'b0};
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PERIPH_TX_CTRL : prdata_pre = {periph_tx_req_reg, 1'b0};
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PERIPH_TX_CTRL : prdata_pre = {periph_tx_req_reg, 1'b0};
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IDLE : prdata_pre = {{30{1'b0}}, core0_idle};
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IDLE : prdata_pre = {{30{1'b0}}, core0_idle};
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USER_DEF_STAT : prdata_pre = user_def_stat;
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USER_DEF_STAT : prdata_pre = user_def_stat;
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USER_DEF0_STAT0 : prdata_pre = user_def0_stat0;
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USER_DEF0_STAT0 : prdata_pre = user_def0_stat0;
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USER_DEF0_STAT1 : prdata_pre = user_def0_stat1;
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USER_DEF0_STAT1 : prdata_pre = user_def0_stat1;
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default : prdata_pre = {32{1'b0}};
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default : prdata_pre = {32{1'b0}};
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endcase
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endcase
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end
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end
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always @(/*AUTOSENSE*/gpaddr or gpread or gpwrite or psel)
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always @(/*AUTOSENSE*/gpaddr or gpread or gpwrite or psel)
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begin
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begin
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pslverr_pre = 1'b0;
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pslverr_pre = 1'b0;
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case (gpaddr)
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case (gpaddr)
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PROC0_STATUS : pslverr_pre = gpwrite; //read only
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PROC0_STATUS : pslverr_pre = gpwrite; //read only
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CORE0_JOINT : pslverr_pre = 1'b0; //read and write
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CORE0_JOINT : pslverr_pre = 1'b0; //read and write
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CORE0_PRIO : pslverr_pre = 1'b0; //read and write
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CORE0_PRIO : pslverr_pre = 1'b0; //read and write
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CORE0_CLKDIV : pslverr_pre = 1'b0; //read and write
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CORE0_CLKDIV : pslverr_pre = 1'b0; //read and write
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CORE0_START : pslverr_pre = gpread; //write only
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CORE0_START : pslverr_pre = gpread; //write only
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PERIPH_RX_CTRL : pslverr_pre = 1'b0; //read and write
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PERIPH_RX_CTRL : pslverr_pre = 1'b0; //read and write
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PERIPH_TX_CTRL : pslverr_pre = 1'b0; //read and write
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PERIPH_TX_CTRL : pslverr_pre = 1'b0; //read and write
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IDLE : pslverr_pre = gpwrite; //read only
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IDLE : pslverr_pre = gpwrite; //read only
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USER_DEF_STAT : pslverr_pre = gpwrite; //read only
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USER_DEF_STAT : pslverr_pre = gpwrite; //read only
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USER_DEF0_STAT0 : pslverr_pre = gpwrite; //read only
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USER_DEF0_STAT0 : pslverr_pre = gpwrite; //read only
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USER_DEF0_STAT1 : pslverr_pre = gpwrite; //read only
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USER_DEF0_STAT1 : pslverr_pre = gpwrite; //read only
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default : pslverr_pre = psel; //decode error
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default : pslverr_pre = psel; //decode error
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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prdata <= #1 {32{1'b0}};
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prdata <= #1 {32{1'b0}};
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else if (gpread & pclken)
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else if (gpread & pclken)
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prdata <= #1 prdata_pre;
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prdata <= #1 prdata_pre;
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else if (pclken) //zero to allow or in apb_mux
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else if (pclken) //zero to allow or in apb_mux
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prdata <= #1 {32{1'b0}};
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prdata <= #1 {32{1'b0}};
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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pslverr <= #1 1'b0;
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pslverr <= #1 1'b0;
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else if ((gpread | gpwrite) & pclken)
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else if ((gpread | gpwrite) & pclken)
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pslverr <= #1 pslverr_pre;
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pslverr <= #1 pslverr_pre;
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else if (pclken)
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else if (pclken)
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pslverr <= #1 1'b0;
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pslverr <= #1 1'b0;
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endmodule
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endmodule
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