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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//---------------------------------------------------------
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//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:53 2011
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//-- Invoked Fri Mar 25 23:36:53 2011
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//--
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//--
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//-- Source file: dma_reg_core.v
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//-- Source file: dma_reg_core.v
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//---------------------------------------------------------
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//---------------------------------------------------------
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module dma_axi64_reg_core0(clk,reset,wr_joint,wr_clkdiv,wr_start,wr_prio,pwdata,clkdiv,ch_start,joint_mode,rd_prio_top,rd_prio_high,rd_prio_top_num,rd_prio_high_num,wr_prio_top,wr_prio_high,wr_prio_top_num,wr_prio_high_num,user_def_stat0,user_def_stat1,ch_int_all_proc,proc0_int_stat);
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module dma_axi64_reg_core0(clk,reset,wr_joint,wr_clkdiv,wr_start,wr_prio,pwdata,clkdiv,ch_start,joint_mode,rd_prio_top,rd_prio_high,rd_prio_top_num,rd_prio_high_num,wr_prio_top,wr_prio_high,wr_prio_top_num,wr_prio_high_num,user_def_stat0,user_def_stat1,ch_int_all_proc,proc0_int_stat);
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input clk;
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input clk;
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input reset;
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input reset;
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input wr_joint;
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input wr_joint;
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input wr_clkdiv;
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input wr_clkdiv;
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input wr_start;
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input wr_start;
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input wr_prio;
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input wr_prio;
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input [31:0] pwdata;
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input [31:0] pwdata;
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output [3:0] clkdiv;
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output [3:0] clkdiv;
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output [7:0] ch_start;
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output [7:0] ch_start;
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output joint_mode;
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output joint_mode;
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output rd_prio_top;
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output rd_prio_top;
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output rd_prio_high;
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output rd_prio_high;
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output [2:0] rd_prio_top_num;
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output [2:0] rd_prio_top_num;
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output [2:0] rd_prio_high_num;
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output [2:0] rd_prio_high_num;
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output wr_prio_top;
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output wr_prio_top;
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output wr_prio_high;
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output wr_prio_high;
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output [2:0] wr_prio_top_num;
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output [2:0] wr_prio_top_num;
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output [2:0] wr_prio_high_num;
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output [2:0] wr_prio_high_num;
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output [31:0] user_def_stat0;
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output [31:0] user_def_stat0;
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output [31:0] user_def_stat1;
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output [31:0] user_def_stat1;
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input [8*1-1:0] ch_int_all_proc;
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input [8*1-1:0] ch_int_all_proc;
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output [7:0] proc0_int_stat;
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output [7:0] proc0_int_stat;
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wire user_def_clkdiv;
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wire user_def_clkdiv;
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wire user_def_bus_32;
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wire user_def_bus_32;
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wire [3:0] user_def_ch_num;
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wire [3:0] user_def_ch_num;
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wire [3:0] user_def_fifo_size;
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wire [3:0] user_def_fifo_size;
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wire [3:0] user_def_wcmd_depth;
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wire [3:0] user_def_wcmd_depth;
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wire [3:0] user_def_rcmd_depth;
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wire [3:0] user_def_rcmd_depth;
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wire user_def_block;
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wire user_def_block;
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wire user_def_wait;
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wire user_def_wait;
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wire user_def_outs;
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wire user_def_outs;
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wire user_def_prio;
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wire user_def_prio;
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wire user_def_tokens;
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wire user_def_tokens;
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wire user_def_timeout;
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wire user_def_timeout;
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wire user_def_wdt;
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wire user_def_wdt;
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wire user_def_joint;
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wire user_def_joint;
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wire user_def_simul;
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wire user_def_simul;
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wire user_def_periph;
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wire user_def_periph;
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wire user_def_lists;
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wire user_def_lists;
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wire user_def_end;
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wire user_def_end;
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wire [5:0] user_def_addr_bits; //max 32
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wire [5:0] user_def_addr_bits; //max 32
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wire [4:0] user_def_buff_bits; //max 16
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wire [4:0] user_def_buff_bits; //max 16
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reg joint_mode;
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reg joint_mode;
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assign user_def_clkdiv = 0;
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assign user_def_clkdiv = 0;
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assign user_def_bus_32 = 0;
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assign user_def_bus_32 = 0;
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assign user_def_ch_num = 1;
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assign user_def_ch_num = 1;
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assign user_def_fifo_size = 5;
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assign user_def_fifo_size = 5;
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assign user_def_wcmd_depth = 2;
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assign user_def_wcmd_depth = 2;
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assign user_def_rcmd_depth = 2;
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assign user_def_rcmd_depth = 2;
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assign user_def_block = 0;
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assign user_def_block = 0;
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assign user_def_wait = 0;
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assign user_def_wait = 0;
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assign user_def_outs = 0;
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assign user_def_outs = 0;
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assign user_def_prio = 0;
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assign user_def_prio = 0;
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assign user_def_tokens = 1;
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assign user_def_tokens = 1;
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assign user_def_timeout = 1;
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assign user_def_timeout = 1;
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assign user_def_wdt = 1;
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assign user_def_wdt = 1;
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assign user_def_joint = 1;
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assign user_def_joint = 1;
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assign user_def_simul = 1;
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assign user_def_simul = 1;
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assign user_def_periph = 1;
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assign user_def_periph = 1;
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assign user_def_lists = 1;
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assign user_def_lists = 1;
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assign user_def_end = 1;
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assign user_def_end = 1;
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assign user_def_addr_bits = 32;
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assign user_def_addr_bits = 32;
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assign user_def_buff_bits = 10;
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assign user_def_buff_bits = 10;
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assign user_def_stat0 =
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assign user_def_stat0 =
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{
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{
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3'b000, //[31:29]
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3'b000, //[31:29]
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user_def_buff_bits, //[28:24]
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user_def_buff_bits, //[28:24]
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1'b0, //[23]
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1'b0, //[23]
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user_def_bus_32, //[22]
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user_def_bus_32, //[22]
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user_def_addr_bits, //[21:16]
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user_def_addr_bits, //[21:16]
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user_def_rcmd_depth, //[15:12]
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user_def_rcmd_depth, //[15:12]
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user_def_wcmd_depth, //[11:8]
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user_def_wcmd_depth, //[11:8]
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user_def_fifo_size, //[7:4]
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user_def_fifo_size, //[7:4]
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user_def_ch_num //[3:0]
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user_def_ch_num //[3:0]
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};
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};
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assign user_def_stat1 =
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assign user_def_stat1 =
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{
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{
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{21{1'b0}}, //[31:13]
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{21{1'b0}}, //[31:13]
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user_def_clkdiv, //[12]
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user_def_clkdiv, //[12]
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user_def_end, //[11]
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user_def_end, //[11]
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user_def_lists, //[10]
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user_def_lists, //[10]
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user_def_periph, //[9]
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user_def_periph, //[9]
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user_def_simul, //[8]
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user_def_simul, //[8]
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user_def_joint, //[7]
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user_def_joint, //[7]
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user_def_block, //[6]
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user_def_block, //[6]
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user_def_wait, //[5]
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user_def_wait, //[5]
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user_def_outs, //[4]
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user_def_outs, //[4]
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user_def_prio, //[3]
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user_def_prio, //[3]
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user_def_tokens, //[2]
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user_def_tokens, //[2]
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user_def_timeout, //[1]
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user_def_timeout, //[1]
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user_def_wdt //[0]
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user_def_wdt //[0]
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};
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};
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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joint_mode <= #1 1'b0;
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joint_mode <= #1 1'b0;
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end
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end
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else if (wr_joint)
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else if (wr_joint)
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begin
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begin
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joint_mode <= #1 pwdata[0];
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joint_mode <= #1 pwdata[0];
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end
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end
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assign rd_prio_top = 'd0;
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assign rd_prio_top = 'd0;
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assign rd_prio_high = 'd0;
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assign rd_prio_high = 'd0;
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assign rd_prio_top_num = 'd0;
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assign rd_prio_top_num = 'd0;
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assign rd_prio_high_num = 'd0;
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assign rd_prio_high_num = 'd0;
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assign wr_prio_top = 'd0;
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assign wr_prio_top = 'd0;
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assign wr_prio_high = 'd0;
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assign wr_prio_high = 'd0;
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assign wr_prio_top_num = 'd0;
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assign wr_prio_top_num = 'd0;
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assign wr_prio_high_num = 'd0;
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assign wr_prio_high_num = 'd0;
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assign clkdiv = 4'd0;
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assign clkdiv = 4'd0;
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assign ch_start = {8{wr_start}} & pwdata[7:0];
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assign ch_start = {8{wr_start}} & pwdata[7:0];
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//interrupt
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//interrupt
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prgen_scatter8_1 #(0) scatter_proc0(.ch_x(ch_int_all_proc), .x(proc0_int_stat));
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prgen_scatter8_1 #(0) scatter_proc0(.ch_x(ch_int_all_proc), .x(proc0_int_stat));
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endmodule
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endmodule
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