The verilog files, fpu_addsub.v and fpu_mul.v, are pipelined versions of
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The verilog files, fpu_addsub.v and fpu_mul.v, are pipelined versions of
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floating point operators. The four rounding modes (Nearest, To Zero, To
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floating point operators. The four rounding modes (Nearest, To Zero, To
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Positive Infintiy, To Negative Infinity) are supported by these operators.
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Positive Infintiy, To Negative Infinity) are supported by these operators.
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Denormalized numbers are not supported, but instead are treated as 0.
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Denormalized numbers are not supported, but instead are treated as 0.
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If infinity or NaN is on either of the inputs,
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If infinity or NaN is on either of the inputs,
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then infinity will be the output. Addition and subtraction have a latency
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then infinity will be the output. Addition and subtraction have a latency
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of 24 clock cycles, and then an output is available on each clock cycle after the latency.
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of 24 clock cycles, and then an output is available on each clock cycle after the latency.
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Multiplication has a latency of 21 clock cycles, and
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Multiplication has a latency of 21 clock cycles, and
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then an output is available on each clock cycle after the latency.
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then an output is available on each clock cycle after the latency.
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For addition and subtraction, fpu_addsub.v was synthesized with an estimated
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For addition and subtraction, fpu_addsub.v was synthesized with an estimated
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frequency of 259 MHz for a Virtex5 device. The synthesis results are below.
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frequency of 259 MHz for a Virtex5 device. The synthesis results are below.
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The file, fpu_addsub_TB.v, is the testbench used to simulate fpu_addsub.v.
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The file, fpu_addsub_TB.v, is the testbench used to simulate fpu_addsub.v.
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For multiplication, fpu_mul.v was synthesized with an estimated
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For multiplication, fpu_mul.v was synthesized with an estimated
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frequency of 393 MHz for a Virtex5 device. The synthesis results are below.
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frequency of 393 MHz for a Virtex5 device. The synthesis results are below.
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The file, fpu_mul_TB.v, is the testbench used to simulate fpu_mul.v.
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The file, fpu_mul_TB.v, is the testbench used to simulate fpu_mul.v.
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Please email me any questions.
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Please email me any questions.
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David Lundgren
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David Lundgren
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davidklun@gmail.com
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davidklun@gmail.com
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addsub synthesis results:
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addsub synthesis results:
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---------------------------------------
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---------------------------------------
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Resource Usage Report for fpu_addsub
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Resource Usage Report for fpu_addsub
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Mapping to part: xc5vsx95tff1136-2
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Mapping to part: xc5vsx95tff1136-2
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Cell usage:
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Cell usage:
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FDE 55 uses
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FDE 55 uses
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FDR 6 uses
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FDR 6 uses
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FDRE 2848 uses
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FDRE 2848 uses
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GND 1 use
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GND 1 use
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MUXCY 8 uses
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MUXCY 8 uses
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MUXCY_L 293 uses
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MUXCY_L 293 uses
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VCC 1 use
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VCC 1 use
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XORCY 240 uses
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XORCY 240 uses
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XORCY_L 5 uses
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XORCY_L 5 uses
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LUT1 98 uses
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LUT1 98 uses
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LUT2 377 uses
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LUT2 377 uses
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LUT3 522 uses
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LUT3 522 uses
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LUT4 151 uses
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LUT4 151 uses
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LUT5 101 uses
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LUT5 101 uses
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LUT6 517 uses
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LUT6 517 uses
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I/O ports: 199
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I/O ports: 199
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I/O primitives: 198
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I/O primitives: 198
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IBUF 133 uses
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IBUF 133 uses
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OBUF 65 uses
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OBUF 65 uses
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BUFGP 1 use
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BUFGP 1 use
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SRL primitives:
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SRL primitives:
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SRLC32E 1 use
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SRLC32E 1 use
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SRL16E 54 uses
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SRL16E 54 uses
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I/O Register bits: 0
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I/O Register bits: 0
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Register bits not including I/Os: 2909 (4%)
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Register bits not including I/Os: 2909 (4%)
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Global Clock Buffers: 1 of 32 (3%)
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Global Clock Buffers: 1 of 32 (3%)
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Total load per clock:
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Total load per clock:
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fpu_addsub|clk: 2964
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fpu_addsub|clk: 2964
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Mapping Summary:
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Mapping Summary:
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Total LUTs: 1821 (3%)
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Total LUTs: 1821 (3%)
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------------------------------
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------------------------------
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multiply synthesis results:
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multiply synthesis results:
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---------------------------------------
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---------------------------------------
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Resource Usage Report for fpu_mul
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Resource Usage Report for fpu_mul
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Mapping to part: xc5vsx95tff1136-2
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Mapping to part: xc5vsx95tff1136-2
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Cell usage:
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Cell usage:
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DSP48E 9 uses
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DSP48E 9 uses
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FDE 83 uses
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FDE 83 uses
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FDRE 1536 uses
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FDRE 1536 uses
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FDRSE 11 uses
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FDRSE 11 uses
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GND 1 use
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GND 1 use
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MUXCY 7 uses
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MUXCY 7 uses
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MUXCY_L 164 uses
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MUXCY_L 164 uses
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VCC 1 use
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VCC 1 use
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XORCY 128 uses
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XORCY 128 uses
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XORCY_L 5 uses
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XORCY_L 5 uses
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LUT1 82 uses
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LUT1 82 uses
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LUT2 215 uses
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LUT2 215 uses
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LUT3 170 uses
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LUT3 170 uses
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LUT4 48 uses
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LUT4 48 uses
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LUT5 13 uses
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LUT5 13 uses
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LUT6 32 uses
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LUT6 32 uses
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I/O ports: 198
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I/O ports: 198
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I/O primitives: 197
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I/O primitives: 197
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IBUF 132 uses
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IBUF 132 uses
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OBUF 65 uses
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OBUF 65 uses
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BUFGP 1 use
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BUFGP 1 use
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SRL primitives:
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SRL primitives:
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SRL16E 83 uses
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SRL16E 83 uses
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I/O Register bits: 0
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I/O Register bits: 0
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Register bits not including I/Os: 1630 (2%)
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Register bits not including I/Os: 1630 (2%)
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Global Clock Buffers: 1 of 32 (3%)
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Global Clock Buffers: 1 of 32 (3%)
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Total load per clock:
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Total load per clock:
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fpu_mul|clk: 1722
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fpu_mul|clk: 1722
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Mapping Summary:
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Mapping Summary:
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Total LUTs: 643 (1%)
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Total LUTs: 643 (1%)
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