-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2010
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_components_lib;
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LIBRARY IEEE, common_components_lib;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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-- Purpose:
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-- Purpose:
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-- Hold hld_ctrl active until next ready high when in_ctrl is active while
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-- Hold hld_ctrl active until next ready high when in_ctrl is active while
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-- ready went low
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-- ready went low
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-- Description:
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-- Description:
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-- When ready goes low there may still arrive one new valid data. The control
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-- When ready goes low there may still arrive one new valid data. The control
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-- information for this data can then be held with this component. When ready
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-- information for this data can then be held with this component. When ready
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-- goes high again the held data can then be output and the hld_ctrl is
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-- goes high again the held data can then be output and the hld_ctrl is
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-- released. After that the subsequent data output can come directly from the
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-- released. After that the subsequent data output can come directly from the
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-- up stream source, until ready goes low again.
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-- up stream source, until ready goes low again.
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-- Remarks:
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-- Remarks:
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-- . Ready latency RL = 1
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-- . Ready latency RL = 1
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-- . The in_ctrl is typically in_valid, in_sop or in_eop
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-- . The in_ctrl is typically in_valid, in_sop or in_eop
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-- . Typically used together with dp_hold_data
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-- . Typically used together with dp_hold_data
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ENTITY dp_hold_ctrl IS
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ENTITY dp_hold_ctrl IS
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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ready : IN STD_LOGIC;
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ready : IN STD_LOGIC;
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in_ctrl : IN STD_LOGIC;
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in_ctrl : IN STD_LOGIC;
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hld_ctrl : OUT STD_LOGIC
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hld_ctrl : OUT STD_LOGIC
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);
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);
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END dp_hold_ctrl;
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END dp_hold_ctrl;
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ARCHITECTURE rtl OF dp_hold_ctrl IS
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ARCHITECTURE rtl OF dp_hold_ctrl IS
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SIGNAL hi_ctrl : STD_LOGIC;
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SIGNAL hi_ctrl : STD_LOGIC;
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SIGNAL lo_ctrl : STD_LOGIC;
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SIGNAL lo_ctrl : STD_LOGIC;
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BEGIN
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BEGIN
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hi_ctrl <= in_ctrl AND NOT ready; -- capture
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hi_ctrl <= in_ctrl AND NOT ready; -- capture
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lo_ctrl <= NOT in_ctrl AND ready; -- release
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lo_ctrl <= NOT in_ctrl AND ready; -- release
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u_hld_ctrl : ENTITY common_components_lib.common_switch
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u_hld_ctrl : ENTITY common_components_lib.common_switch
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PORT MAP (
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PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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switch_high => hi_ctrl,
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switch_high => hi_ctrl,
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switch_low => lo_ctrl,
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switch_low => lo_ctrl,
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out_level => hld_ctrl
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out_level => hld_ctrl
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);
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);
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END rtl;
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END rtl;
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