-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2010
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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--
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-- This program is free software: you can redistribute it and/or modify
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- it under the terms of the GNU General Public License as published by
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-- you may not use this file except in compliance with the License.
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-- the Free Software Foundation, either version 3 of the License, or
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-- You may obtain a copy of the License at
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- http://www.apache.org/licenses/LICENSE-2.0
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- Unless required by applicable law or agreed to in writing, software
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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-- Purpose:
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-- Purpose:
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-- Typically used in dp_latency_adapter.
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-- Typically used in dp_latency_adapter.
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-- Description:
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-- Description:
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-- Increase the output ready latency by g_incr_latency compared to the input
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-- Increase the output ready latency by g_incr_latency compared to the input
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-- ready latency g_in_latency. Hence the output latency becomes g_in_latency
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-- ready latency g_in_latency. Hence the output latency becomes g_in_latency
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-- + g_incr_latency.
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-- + g_incr_latency.
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-- Remark:
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-- Remark:
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-- . The SOSI data stream signals (i.e. data, empty, channel, err) are passed
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-- . The SOSI data stream signals (i.e. data, empty, channel, err) are passed
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-- on as wires.
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-- on as wires.
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-- . The out_sync, out_val, out_sop and out_eop are internally AND with the
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-- . The out_sync, out_val, out_sop and out_eop are internally AND with the
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-- delayed src_in.ready, this is only truely necessary if the input ready
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-- delayed src_in.ready, this is only truely necessary if the input ready
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-- latency is 0, but it does not harm to do it also when the input ready
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-- latency is 0, but it does not harm to do it also when the input ready
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-- latency > 0. However to easy achieving P&R timing it is better to not have
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-- latency > 0. However to easy achieving P&R timing it is better to not have
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-- unnessary logic in the combinatorial path of out_sync, out_val, out_sop
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-- unnessary logic in the combinatorial path of out_sync, out_val, out_sop
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-- and out_eop, therefore the AND with reg_val is only generated when
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-- and out_eop, therefore the AND with reg_val is only generated when
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-- g_in_latency=0.
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-- g_in_latency=0.
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ENTITY dp_latency_increase IS
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ENTITY dp_latency_increase IS
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GENERIC (
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GENERIC (
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g_in_latency : NATURAL := 0; -- >= 0
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g_in_latency : NATURAL := 0; -- >= 0
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g_incr_latency : NATURAL := 2 -- >= 0
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g_incr_latency : NATURAL := 2 -- >= 0
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);
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);
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PORT (
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PORT (
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rst : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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-- ST sink
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-- ST sink
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snk_out : OUT t_dp_siso;
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snk_out : OUT t_dp_siso;
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snk_in : IN t_dp_sosi;
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snk_in : IN t_dp_sosi;
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-- ST source
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-- ST source
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src_in : IN t_dp_siso;
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src_in : IN t_dp_siso;
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src_out : OUT t_dp_sosi
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src_out : OUT t_dp_sosi
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);
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);
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END dp_latency_increase;
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END dp_latency_increase;
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ARCHITECTURE rtl OF dp_latency_increase IS
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ARCHITECTURE rtl OF dp_latency_increase IS
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CONSTANT c_out_latency : NATURAL := g_in_latency + g_incr_latency;
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CONSTANT c_out_latency : NATURAL := g_in_latency + g_incr_latency;
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SIGNAL reg_ready : STD_LOGIC_VECTOR(c_out_latency DOWNTO 0);
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SIGNAL reg_ready : STD_LOGIC_VECTOR(c_out_latency DOWNTO 0);
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SIGNAL reg_val : STD_LOGIC;
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SIGNAL reg_val : STD_LOGIC;
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SIGNAL i_snk_out : t_dp_siso := c_dp_siso_rdy;
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SIGNAL i_snk_out : t_dp_siso := c_dp_siso_rdy;
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BEGIN
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BEGIN
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-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
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-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
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snk_out <= i_snk_out;
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snk_out <= i_snk_out;
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-- Support wires only for g_incr_latency=0
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-- Support wires only for g_incr_latency=0
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no_latency : IF g_incr_latency=0 GENERATE
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no_latency : IF g_incr_latency=0 GENERATE
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i_snk_out <= src_in; -- SISO
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i_snk_out <= src_in; -- SISO
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src_out <= snk_in; -- SOSI
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src_out <= snk_in; -- SOSI
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END GENERATE no_latency;
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END GENERATE no_latency;
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gen_latency : IF g_incr_latency>0 GENERATE
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gen_latency : IF g_incr_latency>0 GENERATE
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-- SISO
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-- SISO
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reg_ready(0) <= src_in.ready; -- use reg_ready(0) to combinatorially store src_in.ready
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reg_ready(0) <= src_in.ready; -- use reg_ready(0) to combinatorially store src_in.ready
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p_clk : PROCESS(rst, clk)
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p_clk : PROCESS(rst, clk)
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BEGIN
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BEGIN
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IF rst='1' THEN
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IF rst='1' THEN
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reg_ready(c_out_latency DOWNTO 1) <= (OTHERS=>'0');
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reg_ready(c_out_latency DOWNTO 1) <= (OTHERS=>'0');
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ELSIF rising_edge(clk) THEN
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ELSIF rising_edge(clk) THEN
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reg_ready(c_out_latency DOWNTO 1) <= reg_ready(c_out_latency-1 DOWNTO 0);
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reg_ready(c_out_latency DOWNTO 1) <= reg_ready(c_out_latency-1 DOWNTO 0);
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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i_snk_out.xon <= src_in.xon; -- Pass on frame level flow control
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i_snk_out.xon <= src_in.xon; -- Pass on frame level flow control
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i_snk_out.ready <= reg_ready(g_incr_latency); -- Adjust ready latency
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i_snk_out.ready <= reg_ready(g_incr_latency); -- Adjust ready latency
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-- SOSI
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-- SOSI
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gen_out : IF g_in_latency/=0 GENERATE
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gen_out : IF g_in_latency/=0 GENERATE
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src_out <= snk_in;
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src_out <= snk_in;
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END GENERATE;
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END GENERATE;
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gen_zero_out : IF g_in_latency=0 GENERATE
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gen_zero_out : IF g_in_latency=0 GENERATE
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reg_val <= reg_ready(c_out_latency);
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reg_val <= reg_ready(c_out_latency);
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p_src_out : PROCESS(snk_in, reg_val)
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p_src_out : PROCESS(snk_in, reg_val)
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BEGIN
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BEGIN
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src_out <= snk_in;
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src_out <= snk_in;
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src_out.sync <= snk_in.sync AND reg_val;
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src_out.sync <= snk_in.sync AND reg_val;
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src_out.valid <= snk_in.valid AND reg_val;
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src_out.valid <= snk_in.valid AND reg_val;
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src_out.sop <= snk_in.sop AND reg_val;
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src_out.sop <= snk_in.sop AND reg_val;
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src_out.eop <= snk_in.eop AND reg_val;
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src_out.eop <= snk_in.eop AND reg_val;
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END PROCESS;
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END PROCESS;
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END GENERATE;
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END GENERATE;
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END GENERATE gen_latency;
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END GENERATE gen_latency;
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END rtl;
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END rtl;
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