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ECO32 Architecture
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ECO32 Architecture
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==================
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General
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General
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The ECO32 is a general purpose 32-bit integer processor.
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The ECO32 is a general purpose 32-bit integer processor.
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It is a big endian machine with a byte addressable memory.
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It is a big endian machine with a byte addressable memory.
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32 integer registers (each 32 bits wide) are provided
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32 integer registers (each 32 bits wide) are provided
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within the CPU. The data path is 32 bits wide. Each machine
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within the CPU. The data path is 32 bits wide. Each machine
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instruction is stored in a single 32 bit word. Addresses as
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instruction is stored in a single 32 bit word. Addresses as
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generated by a program are 32 bits wide.
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generated by a program are 32 bits wide.
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The CPU can operate in one of two modes, kernel or user mode.
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The CPU can operate in one of two modes, kernel or user mode.
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When running in user mode, certain operations are illegal
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When running in user mode, certain operations are illegal
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and result in an exception when the program tries to execute
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and result in an exception when the program tries to execute
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such an operation.
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such an operation.
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Memory addresses as generated by a running program are virtual
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Memory addresses as generated by a running program are virtual
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addresses; a memory management unit (which is part of the CPU)
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addresses; a memory management unit (which is part of the CPU)
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converts these into physical addresses. The unit of translation
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converts these into physical addresses. The unit of translation
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is called a page. Pages are 4096 bytes in size. The hardware
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is called a page. Pages are 4096 bytes in size. The hardware
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support for paging is minimalistic: only a TLB is provided.
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support for paging is minimalistic: only a TLB is provided.
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This implies a wide range of possibilities for the operating
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This implies a wide range of possibilities for the operating
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system designer how to manage page tables.
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system designer how to manage page tables.
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The ECO32 is a RISC processor strongly resembling MIPS.
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The ECO32 is a RISC processor strongly resembling MIPS.
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It references memory (and thus I/O) only by load and store
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It references memory (and thus I/O) only by load and store
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instructions. Instructions operating on data usually come
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instructions. Instructions operating on data usually come
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in two forms: either with two source registers and a target
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in two forms: either with two source registers and a target
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register, or a 16 bit wide immediate constant (coded within
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register, or a 16 bit wide immediate constant (coded within
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the instruction) instead of the second source register. All
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the instruction) instead of the second source register. All
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operations on data are carried out on all 32 bits ("word")
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operations on data are carried out on all 32 bits ("word")
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in parallel; the load and store instructions can also transfer
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in parallel; the load and store instructions can also transfer
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16 bits ("half-word") and 8 bits ("byte"). Memory access to
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16 bits ("half-word") and 8 bits ("byte"). Memory access to
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words must be aligned on word boundaries (addresses are evenly
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words must be aligned on word boundaries (addresses are evenly
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divisible by 4); access to half-words must be aligned on
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divisible by 4); access to half-words must be aligned on
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half-word boundaries (addresses are evenly divisible by 2).
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half-word boundaries (addresses are evenly divisible by 2).
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The load instructions dealing with half-words and bytes can
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The load instructions dealing with half-words and bytes can
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either sign-extend their data or zero-extend it. All the load
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either sign-extend their data or zero-extend it. All the load
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and store instructions do only use one single addressing mode.
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and store instructions do only use one single addressing mode.
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The memory address is computed as the sum of the contents of
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The memory address is computed as the sum of the contents of
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a general purpose register and a sign-extended 16 bit immediate
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a general purpose register and a sign-extended 16 bit immediate
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offset coded within the instruction.
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offset coded within the instruction.
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Physical Address Space Utilisation
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Physical Address Space Utilisation
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The main memory extends from address 0 to MEMORY_SIZE,
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The main memory extends from address 0 to MEMORY_SIZE,
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which has an upper limit of 512 MB. The ROM is located
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which has an upper limit of 512 MB. The ROM is located
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at 0x20000000; its size, ROM_SIZE, is at most 256 MB.
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at 0x20000000; its size, ROM_SIZE, is at most 256 MB.
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The I/O is memory-mapped and located at 0x30000000; its
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The I/O is memory-mapped and located at 0x30000000; its
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size is again at most 256 MB. The I/O address space is
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size is again at most 256 MB. The I/O address space is
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divided evenly into 256 devices; each device may occupy
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divided evenly into 256 devices; each device may occupy
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up to 1 MB of address space.
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up to 1 MB of address space.
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Virtual Address Space Utilisation
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Virtual Address Space Utilisation
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---------------------------------
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---------------------------------
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Registers
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Registers
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The 32 general purpose registers $0..$31 are 32 bits wide. The
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The 32 general purpose registers $0..$31 are 32 bits wide. The
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value of $0 is always 0; write operations to this register don't
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value of $0 is always 0; write operations to this register don't
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have any effect. Procedure calls place their return address in
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have any effect. Procedure calls place their return address in
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register $31. Interrupts and exceptions place the address of the
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register $31. Interrupts and exceptions place the address of the
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next instruction (in case of an interrupt) or the address of the
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next instruction (in case of an interrupt) or the address of the
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offending instruction (in case of an exception) in register $30.
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offending instruction (in case of an exception) in register $30.
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