//
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//
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// eco32.v -- ECO32 top-level description
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// eco32.v -- ECO32 top-level description
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//
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//
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module eco32(clk_in,
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module eco32(clk_in,
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reset_inout_n,
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reset_inout_n,
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sdram_clk,
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sdram_clk,
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sdram_fb,
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sdram_fb,
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sdram_cke,
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sdram_cke,
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sdram_cs_n,
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sdram_cs_n,
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sdram_ras_n,
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sdram_ras_n,
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sdram_cas_n,
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sdram_cas_n,
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sdram_we_n,
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sdram_we_n,
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sdram_ba,
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sdram_ba,
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sdram_a,
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sdram_a,
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sdram_udqm,
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sdram_udqm,
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sdram_ldqm,
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sdram_ldqm,
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sdram_dq,
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sdram_dq,
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flash_ce_n,
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flash_ce_n,
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flash_oe_n,
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flash_oe_n,
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flash_we_n,
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flash_we_n,
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flash_rst_n,
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flash_rst_n,
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flash_byte_n,
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flash_byte_n,
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flash_a,
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flash_a,
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flash_d,
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flash_d,
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vga_hsync,
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vga_hsync,
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vga_vsync,
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vga_vsync,
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vga_r,
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vga_r,
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vga_g,
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vga_g,
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vga_b,
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vga_b,
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ps2_clk,
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ps2_clk,
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ps2_data,
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ps2_data,
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rs232_0_rxd,
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rs232_0_rxd,
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rs232_0_txd,
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rs232_0_txd,
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rs232_1_rxd,
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rs232_1_rxd,
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rs232_1_txd,
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rs232_1_txd,
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pbus_d,
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pbus_d,
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pbus_a,
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pbus_a,
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pbus_read_n,
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pbus_read_n,
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pbus_write_n,
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pbus_write_n,
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ata_cs0_n,
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ata_cs0_n,
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ata_cs1_n,
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ata_cs1_n,
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ata_intrq,
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ata_intrq,
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ata_dmarq,
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ata_dmarq,
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ata_dmack_n,
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ata_dmack_n,
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ata_iordy,
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ata_iordy,
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slot1_cs_n,
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slot1_cs_n,
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slot2_cs_n,
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slot2_cs_n,
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ether_cs_n);
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ether_cs_n);
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// clock and reset
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// clock and reset
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input clk_in;
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input clk_in;
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inout reset_inout_n;
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inout reset_inout_n;
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// SDRAM
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// SDRAM
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output sdram_clk;
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output sdram_clk;
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input sdram_fb;
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input sdram_fb;
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output sdram_cke;
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output sdram_cke;
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output sdram_cs_n;
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output sdram_cs_n;
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output sdram_ras_n;
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output sdram_ras_n;
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output sdram_cas_n;
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output sdram_cas_n;
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output sdram_we_n;
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output sdram_we_n;
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output [1:0] sdram_ba;
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output [1:0] sdram_ba;
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output [12:0] sdram_a;
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output [12:0] sdram_a;
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output sdram_udqm;
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output sdram_udqm;
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output sdram_ldqm;
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output sdram_ldqm;
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inout [15:0] sdram_dq;
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inout [15:0] sdram_dq;
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// flash ROM
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// flash ROM
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output flash_ce_n;
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output flash_ce_n;
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output flash_oe_n;
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output flash_oe_n;
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output flash_we_n;
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output flash_we_n;
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output flash_rst_n;
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output flash_rst_n;
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output flash_byte_n;
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output flash_byte_n;
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output [19:0] flash_a;
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output [19:0] flash_a;
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input [15:0] flash_d;
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input [15:0] flash_d;
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// VGA display
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// VGA display
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output vga_hsync;
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output vga_hsync;
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output vga_vsync;
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output vga_vsync;
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output [2:0] vga_r;
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output [2:0] vga_r;
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output [2:0] vga_g;
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output [2:0] vga_g;
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output [2:0] vga_b;
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output [2:0] vga_b;
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// keyboard
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// keyboard
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input ps2_clk;
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input ps2_clk;
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input ps2_data;
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input ps2_data;
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// serial line 0
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// serial line 0
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input rs232_0_rxd;
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input rs232_0_rxd;
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output rs232_0_txd;
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output rs232_0_txd;
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// serial line 1
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// serial line 1
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input rs232_1_rxd;
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input rs232_1_rxd;
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output rs232_1_txd;
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output rs232_1_txd;
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// peripheral bus
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// peripheral bus
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inout [15:0] pbus_d;
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inout [15:0] pbus_d;
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output [4:0] pbus_a;
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output [4:0] pbus_a;
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output pbus_read_n;
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output pbus_read_n;
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output pbus_write_n;
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output pbus_write_n;
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// ATA adapter
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// ATA adapter
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output ata_cs0_n;
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output ata_cs0_n;
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output ata_cs1_n;
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output ata_cs1_n;
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input ata_intrq;
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input ata_intrq;
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input ata_dmarq;
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input ata_dmarq;
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output ata_dmack_n;
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output ata_dmack_n;
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input ata_iordy;
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input ata_iordy;
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// expansion slot 1
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// expansion slot 1
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output slot1_cs_n;
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output slot1_cs_n;
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// expansion slot 2
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// expansion slot 2
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output slot2_cs_n;
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output slot2_cs_n;
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// ethernet
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// ethernet
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output ether_cs_n;
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output ether_cs_n;
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// clk_reset
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// clk_reset
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wire clk;
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wire clk;
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wire clk_ok;
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wire clk_ok;
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wire reset;
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wire reset;
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// cpu
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// cpu
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wire cpu_en;
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wire cpu_en;
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wire cpu_wr;
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wire cpu_wr;
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wire [1:0] cpu_size;
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wire [1:0] cpu_size;
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wire [31:0] cpu_addr;
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wire [31:0] cpu_addr;
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wire [31:0] cpu_data_in;
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wire [31:0] cpu_data_in;
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wire [31:0] cpu_data_out;
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wire [31:0] cpu_data_out;
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wire cpu_wt;
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wire cpu_wt;
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wire [15:0] cpu_irq;
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wire [15:0] cpu_irq;
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// ram
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// ram
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wire ram_en;
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wire ram_en;
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wire ram_wr;
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wire ram_wr;
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wire [1:0] ram_size;
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wire [1:0] ram_size;
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wire [24:0] ram_addr;
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wire [24:0] ram_addr;
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wire [31:0] ram_data_in;
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wire [31:0] ram_data_in;
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wire [31:0] ram_data_out;
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wire [31:0] ram_data_out;
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wire ram_wt;
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wire ram_wt;
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// rom
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// rom
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wire rom_en;
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wire rom_en;
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wire rom_wr;
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wire rom_wr;
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wire [1:0] rom_size;
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wire [1:0] rom_size;
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wire [20:0] rom_addr;
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wire [20:0] rom_addr;
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wire [31:0] rom_data_out;
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wire [31:0] rom_data_out;
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wire rom_wt;
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wire rom_wt;
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// tmr0
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// tmr0
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wire tmr0_en;
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wire tmr0_en;
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wire tmr0_wr;
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wire tmr0_wr;
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wire [3:2] tmr0_addr;
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wire [3:2] tmr0_addr;
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wire [31:0] tmr0_data_in;
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wire [31:0] tmr0_data_in;
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wire [31:0] tmr0_data_out;
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wire [31:0] tmr0_data_out;
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wire tmr0_wt;
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wire tmr0_wt;
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wire tmr0_irq;
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wire tmr0_irq;
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// tmr1
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// tmr1
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wire tmr1_en;
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wire tmr1_en;
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wire tmr1_wr;
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wire tmr1_wr;
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wire [3:2] tmr1_addr;
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wire [3:2] tmr1_addr;
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wire [31:0] tmr1_data_in;
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wire [31:0] tmr1_data_in;
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wire [31:0] tmr1_data_out;
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wire [31:0] tmr1_data_out;
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wire tmr1_wt;
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wire tmr1_wt;
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wire tmr1_irq;
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wire tmr1_irq;
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// dsp
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// dsp
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wire dsp_en;
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wire dsp_en;
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wire dsp_wr;
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wire dsp_wr;
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wire [13:2] dsp_addr;
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wire [13:2] dsp_addr;
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wire [15:0] dsp_data_in;
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wire [15:0] dsp_data_in;
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wire [15:0] dsp_data_out;
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wire [15:0] dsp_data_out;
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wire dsp_wt;
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wire dsp_wt;
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// kbd
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// kbd
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wire kbd_en;
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wire kbd_en;
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wire kbd_wr;
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wire kbd_wr;
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wire kbd_addr;
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wire kbd_addr;
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wire [7:0] kbd_data_in;
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wire [7:0] kbd_data_in;
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wire [7:0] kbd_data_out;
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wire [7:0] kbd_data_out;
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wire kbd_wt;
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wire kbd_wt;
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wire kbd_irq;
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wire kbd_irq;
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// ser0
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// ser0
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wire ser0_en;
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wire ser0_en;
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wire ser0_wr;
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wire ser0_wr;
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wire [3:2] ser0_addr;
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wire [3:2] ser0_addr;
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wire [7:0] ser0_data_in;
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wire [7:0] ser0_data_in;
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wire [7:0] ser0_data_out;
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wire [7:0] ser0_data_out;
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wire ser0_wt;
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wire ser0_wt;
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wire ser0_irq_r;
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wire ser0_irq_r;
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wire ser0_irq_t;
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wire ser0_irq_t;
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// ser1
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// ser1
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wire ser1_en;
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wire ser1_en;
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wire ser1_wr;
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wire ser1_wr;
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wire [3:2] ser1_addr;
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wire [3:2] ser1_addr;
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wire [7:0] ser1_data_in;
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wire [7:0] ser1_data_in;
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wire [7:0] ser1_data_out;
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wire [7:0] ser1_data_out;
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wire ser1_wt;
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wire ser1_wt;
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wire ser1_irq_r;
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wire ser1_irq_r;
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wire ser1_irq_t;
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wire ser1_irq_t;
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// dsk
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// dsk
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wire dsk_en;
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wire dsk_en;
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wire dsk_wr;
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wire dsk_wr;
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wire [19:2] dsk_addr;
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wire [19:2] dsk_addr;
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wire [31:0] dsk_data_in;
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wire [31:0] dsk_data_in;
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wire [31:0] dsk_data_out;
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wire [31:0] dsk_data_out;
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wire dsk_wt;
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wire dsk_wt;
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wire dsk_irq;
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wire dsk_irq;
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clk_reset clk_reset1(
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clk_reset clk_reset1(
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.clk_in(clk_in),
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.clk_in(clk_in),
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.reset_inout_n(reset_inout_n),
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.reset_inout_n(reset_inout_n),
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.sdram_clk(sdram_clk),
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.sdram_clk(sdram_clk),
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.sdram_fb(sdram_fb),
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.sdram_fb(sdram_fb),
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.clk(clk),
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.clk(clk),
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.clk_ok(clk_ok),
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.clk_ok(clk_ok),
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.reset(reset)
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.reset(reset)
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);
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);
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busctrl busctrl1(
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busctrl busctrl1(
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// cpu
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// cpu
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.cpu_en(cpu_en),
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.cpu_en(cpu_en),
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.cpu_wr(cpu_wr),
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.cpu_wr(cpu_wr),
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.cpu_size(cpu_size[1:0]),
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.cpu_size(cpu_size[1:0]),
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.cpu_addr(cpu_addr[31:0]),
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.cpu_addr(cpu_addr[31:0]),
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.cpu_data_in(cpu_data_in[31:0]),
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.cpu_data_in(cpu_data_in[31:0]),
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.cpu_data_out(cpu_data_out[31:0]),
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.cpu_data_out(cpu_data_out[31:0]),
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.cpu_wt(cpu_wt),
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.cpu_wt(cpu_wt),
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// ram
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// ram
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.ram_en(ram_en),
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.ram_en(ram_en),
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.ram_wr(ram_wr),
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.ram_wr(ram_wr),
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.ram_size(ram_size[1:0]),
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.ram_size(ram_size[1:0]),
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.ram_addr(ram_addr[24:0]),
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.ram_addr(ram_addr[24:0]),
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.ram_data_in(ram_data_in[31:0]),
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.ram_data_in(ram_data_in[31:0]),
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.ram_data_out(ram_data_out[31:0]),
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.ram_data_out(ram_data_out[31:0]),
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.ram_wt(ram_wt),
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.ram_wt(ram_wt),
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// rom
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// rom
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.rom_en(rom_en),
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.rom_en(rom_en),
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.rom_wr(rom_wr),
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.rom_wr(rom_wr),
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.rom_size(rom_size[1:0]),
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.rom_size(rom_size[1:0]),
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.rom_addr(rom_addr[20:0]),
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.rom_addr(rom_addr[20:0]),
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.rom_data_out(rom_data_out[31:0]),
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.rom_data_out(rom_data_out[31:0]),
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.rom_wt(rom_wt),
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.rom_wt(rom_wt),
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// tmr0
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// tmr0
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.tmr0_en(tmr0_en),
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.tmr0_en(tmr0_en),
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.tmr0_wr(tmr0_wr),
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.tmr0_wr(tmr0_wr),
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.tmr0_addr(tmr0_addr[3:2]),
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.tmr0_addr(tmr0_addr[3:2]),
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.tmr0_data_in(tmr0_data_in[31:0]),
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.tmr0_data_in(tmr0_data_in[31:0]),
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.tmr0_data_out(tmr0_data_out[31:0]),
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.tmr0_data_out(tmr0_data_out[31:0]),
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.tmr0_wt(tmr0_wt),
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.tmr0_wt(tmr0_wt),
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// tmr1
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// tmr1
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.tmr1_en(tmr1_en),
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.tmr1_en(tmr1_en),
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.tmr1_wr(tmr1_wr),
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.tmr1_wr(tmr1_wr),
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.tmr1_addr(tmr1_addr[3:2]),
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.tmr1_addr(tmr1_addr[3:2]),
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.tmr1_data_in(tmr1_data_in[31:0]),
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.tmr1_data_in(tmr1_data_in[31:0]),
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.tmr1_data_out(tmr1_data_out[31:0]),
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.tmr1_data_out(tmr1_data_out[31:0]),
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.tmr1_wt(tmr1_wt),
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.tmr1_wt(tmr1_wt),
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// dsp
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// dsp
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.dsp_en(dsp_en),
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.dsp_en(dsp_en),
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.dsp_wr(dsp_wr),
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.dsp_wr(dsp_wr),
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.dsp_addr(dsp_addr[13:2]),
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.dsp_addr(dsp_addr[13:2]),
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.dsp_data_in(dsp_data_in[15:0]),
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.dsp_data_in(dsp_data_in[15:0]),
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.dsp_data_out(dsp_data_out[15:0]),
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.dsp_data_out(dsp_data_out[15:0]),
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.dsp_wt(dsp_wt),
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.dsp_wt(dsp_wt),
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// kbd
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// kbd
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.kbd_en(kbd_en),
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.kbd_en(kbd_en),
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.kbd_wr(kbd_wr),
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.kbd_wr(kbd_wr),
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.kbd_addr(kbd_addr),
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.kbd_addr(kbd_addr),
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.kbd_data_in(kbd_data_in[7:0]),
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.kbd_data_in(kbd_data_in[7:0]),
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.kbd_data_out(kbd_data_out[7:0]),
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.kbd_data_out(kbd_data_out[7:0]),
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.kbd_wt(kbd_wt),
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.kbd_wt(kbd_wt),
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// ser0
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// ser0
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.ser0_en(ser0_en),
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.ser0_en(ser0_en),
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.ser0_wr(ser0_wr),
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.ser0_wr(ser0_wr),
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.ser0_addr(ser0_addr[3:2]),
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.ser0_addr(ser0_addr[3:2]),
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.ser0_data_in(ser0_data_in[7:0]),
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.ser0_data_in(ser0_data_in[7:0]),
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.ser0_data_out(ser0_data_out[7:0]),
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.ser0_data_out(ser0_data_out[7:0]),
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.ser0_wt(ser0_wt),
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.ser0_wt(ser0_wt),
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// ser1
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// ser1
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.ser1_en(ser1_en),
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.ser1_en(ser1_en),
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.ser1_wr(ser1_wr),
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.ser1_wr(ser1_wr),
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.ser1_addr(ser1_addr[3:2]),
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.ser1_addr(ser1_addr[3:2]),
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.ser1_data_in(ser1_data_in[7:0]),
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.ser1_data_in(ser1_data_in[7:0]),
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.ser1_data_out(ser1_data_out[7:0]),
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.ser1_data_out(ser1_data_out[7:0]),
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.ser1_wt(ser1_wt),
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.ser1_wt(ser1_wt),
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// dsk
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// dsk
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.dsk_en(dsk_en),
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.dsk_en(dsk_en),
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.dsk_wr(dsk_wr),
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.dsk_wr(dsk_wr),
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.dsk_addr(dsk_addr[19:2]),
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.dsk_addr(dsk_addr[19:2]),
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.dsk_data_in(dsk_data_in[31:0]),
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.dsk_data_in(dsk_data_in[31:0]),
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.dsk_data_out(dsk_data_out[31:0]),
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.dsk_data_out(dsk_data_out[31:0]),
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.dsk_wt(dsk_wt)
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.dsk_wt(dsk_wt)
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);
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);
|
|
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cpu cpu1(
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cpu cpu1(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.bus_en(cpu_en),
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.bus_en(cpu_en),
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.bus_wr(cpu_wr),
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.bus_wr(cpu_wr),
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.bus_size(cpu_size[1:0]),
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.bus_size(cpu_size[1:0]),
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.bus_addr(cpu_addr[31:0]),
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.bus_addr(cpu_addr[31:0]),
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.bus_data_in(cpu_data_in[31:0]),
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.bus_data_in(cpu_data_in[31:0]),
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.bus_data_out(cpu_data_out[31:0]),
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.bus_data_out(cpu_data_out[31:0]),
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.bus_wt(cpu_wt),
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.bus_wt(cpu_wt),
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.irq(cpu_irq[15:0])
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.irq(cpu_irq[15:0])
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);
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);
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|
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assign cpu_irq[15] = tmr1_irq;
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assign cpu_irq[15] = tmr1_irq;
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assign cpu_irq[14] = tmr0_irq;
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assign cpu_irq[14] = tmr0_irq;
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assign cpu_irq[13] = 1'b0;
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assign cpu_irq[13] = 1'b0;
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assign cpu_irq[12] = 1'b0;
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assign cpu_irq[12] = 1'b0;
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assign cpu_irq[11] = 1'b0;
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assign cpu_irq[11] = 1'b0;
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assign cpu_irq[10] = 1'b0;
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assign cpu_irq[10] = 1'b0;
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assign cpu_irq[ 9] = 1'b0;
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assign cpu_irq[ 9] = 1'b0;
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assign cpu_irq[ 8] = dsk_irq;
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assign cpu_irq[ 8] = dsk_irq;
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assign cpu_irq[ 7] = 1'b0;
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assign cpu_irq[ 7] = 1'b0;
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assign cpu_irq[ 6] = 1'b0;
|
assign cpu_irq[ 6] = 1'b0;
|
assign cpu_irq[ 5] = 1'b0;
|
assign cpu_irq[ 5] = 1'b0;
|
assign cpu_irq[ 4] = kbd_irq;
|
assign cpu_irq[ 4] = kbd_irq;
|
assign cpu_irq[ 3] = ser1_irq_r;
|
assign cpu_irq[ 3] = ser1_irq_r;
|
assign cpu_irq[ 2] = ser1_irq_t;
|
assign cpu_irq[ 2] = ser1_irq_t;
|
assign cpu_irq[ 1] = ser0_irq_r;
|
assign cpu_irq[ 1] = ser0_irq_r;
|
assign cpu_irq[ 0] = ser0_irq_t;
|
assign cpu_irq[ 0] = ser0_irq_t;
|
|
|
ram ram1(
|
ram ram1(
|
.clk(clk),
|
.clk(clk),
|
.clk_ok(clk_ok),
|
.clk_ok(clk_ok),
|
.reset(reset),
|
.reset(reset),
|
.en(ram_en),
|
.en(ram_en),
|
.wr(ram_wr),
|
.wr(ram_wr),
|
.size(ram_size[1:0]),
|
.size(ram_size[1:0]),
|
.addr(ram_addr[24:0]),
|
.addr(ram_addr[24:0]),
|
.data_in(ram_data_in[31:0]),
|
.data_in(ram_data_in[31:0]),
|
.data_out(ram_data_out[31:0]),
|
.data_out(ram_data_out[31:0]),
|
.wt(ram_wt),
|
.wt(ram_wt),
|
.sdram_cke(sdram_cke),
|
.sdram_cke(sdram_cke),
|
.sdram_cs_n(sdram_cs_n),
|
.sdram_cs_n(sdram_cs_n),
|
.sdram_ras_n(sdram_ras_n),
|
.sdram_ras_n(sdram_ras_n),
|
.sdram_cas_n(sdram_cas_n),
|
.sdram_cas_n(sdram_cas_n),
|
.sdram_we_n(sdram_we_n),
|
.sdram_we_n(sdram_we_n),
|
.sdram_ba(sdram_ba[1:0]),
|
.sdram_ba(sdram_ba[1:0]),
|
.sdram_a(sdram_a[12:0]),
|
.sdram_a(sdram_a[12:0]),
|
.sdram_udqm(sdram_udqm),
|
.sdram_udqm(sdram_udqm),
|
.sdram_ldqm(sdram_ldqm),
|
.sdram_ldqm(sdram_ldqm),
|
.sdram_dq(sdram_dq[15:0])
|
.sdram_dq(sdram_dq[15:0])
|
);
|
);
|
|
|
rom rom1(
|
rom rom1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(rom_en),
|
.en(rom_en),
|
.wr(rom_wr),
|
.wr(rom_wr),
|
.size(rom_size[1:0]),
|
.size(rom_size[1:0]),
|
.addr(rom_addr[20:0]),
|
.addr(rom_addr[20:0]),
|
.data_out(rom_data_out[31:0]),
|
.data_out(rom_data_out[31:0]),
|
.wt(rom_wt),
|
.wt(rom_wt),
|
.ce_n(flash_ce_n),
|
.ce_n(flash_ce_n),
|
.oe_n(flash_oe_n),
|
.oe_n(flash_oe_n),
|
.we_n(flash_we_n),
|
.we_n(flash_we_n),
|
.rst_n(flash_rst_n),
|
.rst_n(flash_rst_n),
|
.byte_n(flash_byte_n),
|
.byte_n(flash_byte_n),
|
.a(flash_a[19:0]),
|
.a(flash_a[19:0]),
|
.d(flash_d[15:0])
|
.d(flash_d[15:0])
|
);
|
);
|
|
|
tmr tmr1_0(
|
tmr tmr1_0(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(tmr0_en),
|
.en(tmr0_en),
|
.wr(tmr0_wr),
|
.wr(tmr0_wr),
|
.addr(tmr0_addr[3:2]),
|
.addr(tmr0_addr[3:2]),
|
.data_in(tmr0_data_in[31:0]),
|
.data_in(tmr0_data_in[31:0]),
|
.data_out(tmr0_data_out[31:0]),
|
.data_out(tmr0_data_out[31:0]),
|
.wt(tmr0_wt),
|
.wt(tmr0_wt),
|
.irq(tmr0_irq)
|
.irq(tmr0_irq)
|
);
|
);
|
|
|
tmr tmr1_1(
|
tmr tmr1_1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(tmr1_en),
|
.en(tmr1_en),
|
.wr(tmr1_wr),
|
.wr(tmr1_wr),
|
.addr(tmr1_addr[3:2]),
|
.addr(tmr1_addr[3:2]),
|
.data_in(tmr1_data_in[31:0]),
|
.data_in(tmr1_data_in[31:0]),
|
.data_out(tmr1_data_out[31:0]),
|
.data_out(tmr1_data_out[31:0]),
|
.wt(tmr1_wt),
|
.wt(tmr1_wt),
|
.irq(tmr1_irq)
|
.irq(tmr1_irq)
|
);
|
);
|
|
|
dsp dsp1(
|
dsp dsp1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(dsp_en),
|
.en(dsp_en),
|
.wr(dsp_wr),
|
.wr(dsp_wr),
|
.addr(dsp_addr[13:2]),
|
.addr(dsp_addr[13:2]),
|
.data_in(dsp_data_in[15:0]),
|
.data_in(dsp_data_in[15:0]),
|
.data_out(dsp_data_out[15:0]),
|
.data_out(dsp_data_out[15:0]),
|
.wt(dsp_wt),
|
.wt(dsp_wt),
|
.hsync(vga_hsync),
|
.hsync(vga_hsync),
|
.vsync(vga_vsync),
|
.vsync(vga_vsync),
|
.r(vga_r[2:0]),
|
.r(vga_r[2:0]),
|
.g(vga_g[2:0]),
|
.g(vga_g[2:0]),
|
.b(vga_b[2:0])
|
.b(vga_b[2:0])
|
);
|
);
|
|
|
kbd kbd1(
|
kbd kbd1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(kbd_en),
|
.en(kbd_en),
|
.wr(kbd_wr),
|
.wr(kbd_wr),
|
.addr(kbd_addr),
|
.addr(kbd_addr),
|
.data_in(kbd_data_in[7:0]),
|
.data_in(kbd_data_in[7:0]),
|
.data_out(kbd_data_out[7:0]),
|
.data_out(kbd_data_out[7:0]),
|
.wt(kbd_wt),
|
.wt(kbd_wt),
|
.irq(kbd_irq),
|
.irq(kbd_irq),
|
.ps2_clk(ps2_clk),
|
.ps2_clk(ps2_clk),
|
.ps2_data(ps2_data)
|
.ps2_data(ps2_data)
|
);
|
);
|
|
|
ser ser1_0(
|
ser ser1_0(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(ser0_en),
|
.en(ser0_en),
|
.wr(ser0_wr),
|
.wr(ser0_wr),
|
.addr(ser0_addr[3:2]),
|
.addr(ser0_addr[3:2]),
|
.data_in(ser0_data_in[7:0]),
|
.data_in(ser0_data_in[7:0]),
|
.data_out(ser0_data_out[7:0]),
|
.data_out(ser0_data_out[7:0]),
|
.wt(ser0_wt),
|
.wt(ser0_wt),
|
.irq_r(ser0_irq_r),
|
.irq_r(ser0_irq_r),
|
.irq_t(ser0_irq_t),
|
.irq_t(ser0_irq_t),
|
.rxd(rs232_0_rxd),
|
.rxd(rs232_0_rxd),
|
.txd(rs232_0_txd)
|
.txd(rs232_0_txd)
|
);
|
);
|
|
|
ser ser1_1(
|
ser ser1_1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(ser1_en),
|
.en(ser1_en),
|
.wr(ser1_wr),
|
.wr(ser1_wr),
|
.addr(ser1_addr[3:2]),
|
.addr(ser1_addr[3:2]),
|
.data_in(ser1_data_in[7:0]),
|
.data_in(ser1_data_in[7:0]),
|
.data_out(ser1_data_out[7:0]),
|
.data_out(ser1_data_out[7:0]),
|
.wt(ser1_wt),
|
.wt(ser1_wt),
|
.irq_r(ser1_irq_r),
|
.irq_r(ser1_irq_r),
|
.irq_t(ser1_irq_t),
|
.irq_t(ser1_irq_t),
|
.rxd(rs232_1_rxd),
|
.rxd(rs232_1_rxd),
|
.txd(rs232_1_txd)
|
.txd(rs232_1_txd)
|
);
|
);
|
|
|
dsk dsk1(
|
dsk dsk1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.en(dsk_en),
|
.en(dsk_en),
|
.wr(dsk_wr),
|
.wr(dsk_wr),
|
.addr(dsk_addr[19:2]),
|
.addr(dsk_addr[19:2]),
|
.data_in(dsk_data_in[31:0]),
|
.data_in(dsk_data_in[31:0]),
|
.data_out(dsk_data_out[31:0]),
|
.data_out(dsk_data_out[31:0]),
|
.wt(dsk_wt),
|
.wt(dsk_wt),
|
.irq(dsk_irq),
|
.irq(dsk_irq),
|
.ata_d(pbus_d[15:0]),
|
.ata_d(pbus_d[15:0]),
|
.ata_a(pbus_a[2:0]),
|
.ata_a(pbus_a[2:0]),
|
.ata_cs0_n(ata_cs0_n),
|
.ata_cs0_n(ata_cs0_n),
|
.ata_cs1_n(ata_cs1_n),
|
.ata_cs1_n(ata_cs1_n),
|
.ata_dior_n(pbus_read_n),
|
.ata_dior_n(pbus_read_n),
|
.ata_diow_n(pbus_write_n),
|
.ata_diow_n(pbus_write_n),
|
.ata_intrq(ata_intrq),
|
.ata_intrq(ata_intrq),
|
.ata_dmarq(ata_dmarq),
|
.ata_dmarq(ata_dmarq),
|
.ata_dmack_n(ata_dmack_n),
|
.ata_dmack_n(ata_dmack_n),
|
.ata_iordy(ata_iordy)
|
.ata_iordy(ata_iordy)
|
);
|
);
|
|
|
assign pbus_a[4:3] = 2'b00;
|
assign pbus_a[4:3] = 2'b00;
|
assign slot1_cs_n = 1;
|
assign slot1_cs_n = 1;
|
assign slot2_cs_n = 1;
|
assign slot2_cs_n = 1;
|
assign ether_cs_n = 1;
|
assign ether_cs_n = 1;
|
|
|
endmodule
|
endmodule
|
|
|