\section{System Instructions}
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\section{System Instructions}
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\subsection{TRAP}
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\subsection{TRAP}
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The TRAP instruction triggers a \name{Trap Fault}. It is typically used by user programs to request action from the operating system.
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The TRAP instruction triggers a \name{Trap Fault}. It is typically used by user programs to request action from the operating system.
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System implementer's note: The fault mechanism causes general purpose register \#30 to be loaded with the address of the faulting instruction, that is, the TRAP instruction itself. However, the fault service routine typically wants to return to the instruction immediately following the TRAP instruction, such that the TRAP is not executed again. This can be achieved by adding 4 to the return address in $R_{30}$ in the service routine. See \myref{2}{rfx} for details.
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System implementer's note: The fault mechanism causes general purpose register \#30 to be loaded with the address of the faulting instruction, that is, the TRAP instruction itself. However, the fault service routine typically wants to return to the instruction immediately following the TRAP instruction, such that the TRAP is not executed again. This can be achieved by adding 4 to the return address in $R_{30}$ in the service routine. See \myref{2}{rfx} for details.
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\noargformat{101110}
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\noargformat{101110}
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\begin{effectize}
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\begin{effectize}
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\effect trigger a \name{Trap Fault}
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\effect trigger a \name{Trap Fault}
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\end{effectize}
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\end{effectize}
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\subsection{RFX}
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\subsection{RFX}
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The RFX instruction returns control from an exception service routine to the interrupted program. The return address is taken from general purpose register \#30. The RFX instruction also restores the privilege mode and interrupt enable to the interrupted state by popping the topmost values of the corresponding state stacks in the \pswx. See \myref{2}{psw} and \myref{2}{rfx} for details.
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The RFX instruction returns control from an exception service routine to the interrupted program. The return address is taken from general purpose register \#30. The RFX instruction also restores the privilege mode and interrupt enable to the interrupted state by popping the topmost values of the corresponding state stacks in the \pswx. See \myref{2}{psw} and \myref{2}{rfx} for details.
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\noargformat{101111}
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\noargformat{101111}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect $PC \leftarrow R_{30}$
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\effect $PC \leftarrow R_{30}$
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\effect $I_C \leftarrow I_P$
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\effect $I_C \leftarrow I_P$
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\effect $I_P \leftarrow I_O$
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\effect $I_P \leftarrow I_O$
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\effect $U_C \leftarrow U_P$
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\effect $U_C \leftarrow U_P$
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\effect $U_P \leftarrow U_O$
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\effect $U_P \leftarrow U_O$
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\end{effectize}
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\end{effectize}
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\subsection{MVFS}
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\subsection{MVFS}
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The MVFS transfers the value of a special-purpose register into a general-purpose register. See \myref{2}{special_purpose_registers} for details on the special-purpose registers.
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The MVFS transfers the value of a special-purpose register into a general-purpose register. See \myref{2}{special_purpose_registers} for details on the special-purpose registers.
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\mvspformat{111000}
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\mvspformat{111000}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect If $z$ does not denote a valid special-purpose register, then trigger an \name{Illegal Instruction Fault}
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\effect If $z$ does not denote a valid special-purpose register, then trigger an \name{Illegal Instruction Fault}
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\effect $R_r \leftarrow S_z$
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\effect $R_r \leftarrow S_z$
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\end{effectize}
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\end{effectize}
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\subsection{MVTS}
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\subsection{MVTS}
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The MVFS transfers the value of a general-purpose register into a special-purpose register. See \myref{2}{special_purpose_registers} for details on the special-purpose registers.
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The MVFS transfers the value of a general-purpose register into a special-purpose register. See \myref{2}{special_purpose_registers} for details on the special-purpose registers.
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\mvspformat{111001}
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\mvspformat{111001}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect If $z$ does not denote a valid special-purpose register, then trigger an \name{Illegal Instruction Fault}
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\effect If $z$ does not denote a valid special-purpose register, then trigger an \name{Illegal Instruction Fault}
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\effect $S_z \leftarrow R_r$
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\effect $S_z \leftarrow R_r$
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\end{effectize}
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\end{effectize}
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\subsection{TBS}
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\subsection{TBS}
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The TBS instruction searches the TLB for a mapping for a virtual address specified in the TLB Entry High register ($S_2$) and stores the resulting entry index in the TLB Index register ($S_1$).
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The TBS instruction searches the TLB for a mapping for a virtual address specified in the TLB Entry High register ($S_2$) and stores the resulting entry index in the TLB Index register ($S_1$).
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\noargformat{111010}
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\noargformat{111010}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect $PageNumber \leftarrow S_{2,31..12}$
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\effect $PageNumber \leftarrow S_{2,31..12}$
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\effect if the TLB contains an entry for $PageNumber$ then
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\effect if the TLB contains an entry for $PageNumber$ then
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\begin{itemize}
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\begin{itemize}
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\item[] $S_1 \leftarrow$ (the corresponding TLB entry index)
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\item[] $S_1 \leftarrow$ (the corresponding TLB entry index)
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\end{itemize}
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\end{itemize}
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\effect else
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\effect else
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\begin{itemize}
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\begin{itemize}
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\item[] $S_1 \leftarrow 80000000_{h}$
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\item[] $S_1 \leftarrow 80000000_{h}$
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\end{itemize}
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\end{itemize}
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\end{effectize}
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\end{effectize}
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\textit{Special cases:} The TBS instruction will ``find'' a TLB entry that uses a page number in the direct-mapped virtual address space (C0000000$_h$ through FFFFFFFF$_h$) if the TLB Entry High register contains the corresponding page number. Normal address translation would not find such an entry since it always chooses direct mapping for such addresses.
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\textit{Special cases:} The TBS instruction will ``find'' a TLB entry that uses a page number in the direct-mapped virtual address space (C0000000$_h$ through FFFFFFFF$_h$) if the TLB Entry High register contains the corresponding page number. Normal address translation would not find such an entry since it always chooses direct mapping for such addresses.
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\subsection{TBWR}
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\subsection{TBWR}
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The TBWR instruction replaces a random TLB entry. First, the index of the entry to replace is determined as a random number in the range of non-fixed TLB entries (see \myref{2}{tlb_random}). Then, data from the TLB Entry High and Low registers ($S_2$ and $S_3$) is written into that TLB entry.
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The TBWR instruction replaces a random TLB entry. First, the index of the entry to replace is determined as a random number in the range of non-fixed TLB entries (see \myref{2}{tlb_random}). Then, data from the TLB Entry High and Low registers ($S_2$ and $S_3$) is written into that TLB entry.
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\noargformat{111011}
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\noargformat{111011}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect $X :=$ (random MOD 28) + 4
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\effect $X :=$ (random MOD 28) + 4
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\effect TLB Entry \#$X \leftarrow (S_3, S_2)$
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\effect TLB Entry \#$X \leftarrow (S_3, S_2)$
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\end{effectize}
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\end{effectize}
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\subsection{TBRI}
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\subsection{TBRI}
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The TBRI instruction reads data from a TLB entry indicated by the TLB Index register ($S_1$) into the TLB Entry High and Low registers ($S_2$ and $S_3$).
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The TBRI instruction reads data from a TLB entry indicated by the TLB Index register ($S_1$) into the TLB Entry High and Low registers ($S_2$ and $S_3$).
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\noargformat{111100}
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\noargformat{111100}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect $X := S_1$ MOD 32
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\effect $X := S_1$ MOD 32
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\effect $(S_3, S_2) \leftarrow$ TLB Entry \#$X$
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\effect $(S_3, S_2) \leftarrow$ TLB Entry \#$X$
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\end{effectize}
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\end{effectize}
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\subsection{TBWI}
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\subsection{TBWI}
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The TBWI instruction writes data from the TLB Entry High and Low registers ($S_2$ and $S_3$) into a TLB entry indicated by the TLB Index register ($S_1$).
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The TBWI instruction writes data from the TLB Entry High and Low registers ($S_2$ and $S_3$) into a TLB entry indicated by the TLB Index register ($S_1$).
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\noargformat{111101}
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\noargformat{111101}
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\begin{effectize}
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\begin{effectize}
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\priveffect
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\priveffect
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\effect $X := S_1$ MOD 32
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\effect $X := S_1$ MOD 32
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\effect TLB Entry \#$X \leftarrow (S_3, S_2)$
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\effect TLB Entry \#$X \leftarrow (S_3, S_2)$
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\end{effectize}
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\end{effectize}
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