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//
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//
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// bio.v -- board specific I/O
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// bio.v -- board specific I/O
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//
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//
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module bio(clk, reset,
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module bio(clk, reset,
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en, wr, addr,
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en, wr, addr,
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data_in, data_out,
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data_in, data_out,
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wt,
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wt,
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sw1_1, sw1_2,
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sw1_1, sw1_2,
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sw1_3, sw1_4,
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sw1_3, sw1_4,
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sw2_n, sw3_n);
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sw2_n, sw3_n);
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// internal interface
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// internal interface
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input clk;
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input clk;
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input reset;
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input reset;
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input en;
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input en;
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input wr;
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input wr;
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input addr;
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input addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output [31:0] data_out;
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output [31:0] data_out;
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output wt;
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output wt;
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// external interface
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// external interface
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input sw1_1;
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input sw1_1;
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input sw1_2;
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input sw1_2;
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input sw1_3;
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input sw1_3;
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input sw1_4;
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input sw1_4;
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input sw2_n;
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input sw2_n;
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input sw3_n;
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input sw3_n;
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reg [31:0] bio_out;
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reg [31:0] bio_out;
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wire [31:0] bio_in;
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wire [31:0] bio_in;
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reg sw1_1_p;
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reg sw1_1_p;
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reg sw1_1_s;
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reg sw1_1_s;
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reg sw1_2_p;
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reg sw1_2_p;
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reg sw1_2_s;
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reg sw1_2_s;
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reg sw1_3_p;
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reg sw1_3_p;
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reg sw1_3_s;
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reg sw1_3_s;
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reg sw1_4_p;
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reg sw1_4_p;
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reg sw1_4_s;
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reg sw1_4_s;
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reg sw2_p_n;
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reg sw2_p_n;
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reg sw2_s_n;
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reg sw2_s_n;
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reg sw3_p_n;
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reg sw3_p_n;
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reg sw3_s_n;
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reg sw3_s_n;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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bio_out[31:0] <= 32'h0;
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bio_out[31:0] <= 32'h0;
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end else begin
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end else begin
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if (en & wr & ~addr) begin
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if (en & wr & ~addr) begin
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bio_out[31:0] <= data_in[31:0];
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bio_out[31:0] <= data_in[31:0];
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end
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end
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end
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end
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end
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end
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assign data_out[31:0] =
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assign data_out[31:0] =
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(addr == 0) ? bio_out[31:0] : bio_in[31:0];
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(addr == 0) ? bio_out[31:0] : bio_in[31:0];
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assign wt = 0;
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assign wt = 0;
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always @(posedge clk) begin
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always @(posedge clk) begin
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sw1_1_p <= sw1_1;
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sw1_1_p <= sw1_1;
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sw1_1_s <= sw1_1_p;
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sw1_1_s <= sw1_1_p;
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sw1_2_p <= sw1_2;
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sw1_2_p <= sw1_2;
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sw1_2_s <= sw1_2_p;
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sw1_2_s <= sw1_2_p;
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sw1_3_p <= sw1_3;
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sw1_3_p <= sw1_3;
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sw1_3_s <= sw1_3_p;
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sw1_3_s <= sw1_3_p;
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sw1_4_p <= sw1_4;
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sw1_4_p <= sw1_4;
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sw1_4_s <= sw1_4_p;
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sw1_4_s <= sw1_4_p;
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sw2_p_n <= sw2_n;
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sw2_p_n <= sw2_n;
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sw2_s_n <= sw2_p_n;
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sw2_s_n <= sw2_p_n;
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sw3_p_n <= sw3_n;
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sw3_p_n <= sw3_n;
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sw3_s_n <= sw3_p_n;
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sw3_s_n <= sw3_p_n;
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end
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end
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assign bio_in[31:0] =
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assign bio_in[31:0] =
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{ 26'h0,
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{ 26'h0,
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~sw3_s_n, ~sw2_s_n,
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~sw3_s_n, ~sw2_s_n,
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sw1_4_s, sw1_3_s, sw1_2_s, sw1_1_s };
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sw1_4_s, sw1_3_s, sw1_2_s, sw1_1_s };
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endmodule
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endmodule
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