//
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//
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// dspmem.v -- display memory
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// dspmem.v -- display memory
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//
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//
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module dspmem(rdwr_row, rdwr_col, wr_data, rd_data, en, wr,
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module dspmem(rdwr_row, rdwr_col, wr_data, rd_data, en, wr,
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clk, pixclk,
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clk, pixclk,
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txtrow, txtcol, attcode, chrcode,
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txtrow, txtcol, attcode, chrcode,
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chrrow_in, chrcol_in, blank_in,
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chrrow_in, chrcol_in, blank_in,
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hsync_in, vsync_in, blink_in,
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hsync_in, vsync_in, blink_in,
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chrrow_out, chrcol_out, blank_out,
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chrrow_out, chrcol_out, blank_out,
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hsync_out, vsync_out, blink_out);
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hsync_out, vsync_out, blink_out);
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input [4:0] rdwr_row;
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input [4:0] rdwr_row;
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input [6:0] rdwr_col;
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input [6:0] rdwr_col;
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input [15:0] wr_data;
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input [15:0] wr_data;
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output [15:0] rd_data;
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output [15:0] rd_data;
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input en;
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input en;
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input wr;
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input wr;
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input clk;
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input clk;
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input pixclk;
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input pixclk;
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input [4:0] txtrow;
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input [4:0] txtrow;
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input [6:0] txtcol;
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input [6:0] txtcol;
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output [7:0] attcode;
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output [7:0] attcode;
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output [7:0] chrcode;
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output [7:0] chrcode;
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input [3:0] chrrow_in;
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input [3:0] chrrow_in;
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input [2:0] chrcol_in;
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input [2:0] chrcol_in;
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input blank_in;
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input blank_in;
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input hsync_in;
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input hsync_in;
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input vsync_in;
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input vsync_in;
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input blink_in;
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input blink_in;
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output reg [3:0] chrrow_out;
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output reg [3:0] chrrow_out;
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output reg [2:0] chrcol_out;
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output reg [2:0] chrcol_out;
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output reg blank_out;
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output reg blank_out;
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output reg hsync_out;
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output reg hsync_out;
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output reg vsync_out;
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output reg vsync_out;
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output reg blink_out;
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output reg blink_out;
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wire [11:0] rdwr_addr;
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wire [11:0] rdwr_addr;
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wire [3:0] rdwr_din_n3;
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wire [3:0] rdwr_din_n3;
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wire [3:0] rdwr_din_n2;
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wire [3:0] rdwr_din_n2;
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wire [3:0] rdwr_din_n1;
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wire [3:0] rdwr_din_n1;
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wire [3:0] rdwr_din_n0;
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wire [3:0] rdwr_din_n0;
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wire [3:0] rdwr_dout_n3;
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wire [3:0] rdwr_dout_n3;
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wire [3:0] rdwr_dout_n2;
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wire [3:0] rdwr_dout_n2;
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wire [3:0] rdwr_dout_n1;
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wire [3:0] rdwr_dout_n1;
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wire [3:0] rdwr_dout_n0;
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wire [3:0] rdwr_dout_n0;
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wire [11:0] rfsh_addr;
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wire [11:0] rfsh_addr;
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wire [3:0] rfsh_din_n3;
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wire [3:0] rfsh_din_n3;
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wire [3:0] rfsh_din_n2;
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wire [3:0] rfsh_din_n2;
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wire [3:0] rfsh_din_n1;
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wire [3:0] rfsh_din_n1;
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wire [3:0] rfsh_din_n0;
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wire [3:0] rfsh_din_n0;
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wire [3:0] rfsh_dout_n3;
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wire [3:0] rfsh_dout_n3;
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wire [3:0] rfsh_dout_n2;
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wire [3:0] rfsh_dout_n2;
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wire [3:0] rfsh_dout_n1;
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wire [3:0] rfsh_dout_n1;
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wire [3:0] rfsh_dout_n0;
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wire [3:0] rfsh_dout_n0;
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assign rdwr_addr[11:7] = rdwr_row[4:0];
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assign rdwr_addr[11:7] = rdwr_row[4:0];
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assign rdwr_addr[6:0] = rdwr_col[6:0];
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assign rdwr_addr[6:0] = rdwr_col[6:0];
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assign rdwr_din_n3 = wr_data[15:12];
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assign rdwr_din_n3 = wr_data[15:12];
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assign rdwr_din_n2 = wr_data[11: 8];
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assign rdwr_din_n2 = wr_data[11: 8];
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assign rdwr_din_n1 = wr_data[ 7: 4];
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assign rdwr_din_n1 = wr_data[ 7: 4];
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assign rdwr_din_n0 = wr_data[ 3: 0];
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assign rdwr_din_n0 = wr_data[ 3: 0];
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assign rd_data[15:12] = rdwr_dout_n3;
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assign rd_data[15:12] = rdwr_dout_n3;
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assign rd_data[11: 8] = rdwr_dout_n2;
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assign rd_data[11: 8] = rdwr_dout_n2;
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assign rd_data[ 7: 4] = rdwr_dout_n1;
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assign rd_data[ 7: 4] = rdwr_dout_n1;
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assign rd_data[ 3: 0] = rdwr_dout_n0;
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assign rd_data[ 3: 0] = rdwr_dout_n0;
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assign rfsh_addr[11:7] = txtrow[4:0];
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assign rfsh_addr[11:7] = txtrow[4:0];
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assign rfsh_addr[6:0] = txtcol[6:0];
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assign rfsh_addr[6:0] = txtcol[6:0];
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assign rfsh_din_n3 = 4'b0000;
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assign rfsh_din_n3 = 4'b0000;
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assign rfsh_din_n2 = 4'b0000;
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assign rfsh_din_n2 = 4'b0000;
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assign rfsh_din_n1 = 4'b0000;
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assign rfsh_din_n1 = 4'b0000;
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assign rfsh_din_n0 = 4'b0000;
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assign rfsh_din_n0 = 4'b0000;
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assign attcode[7:4] = rfsh_dout_n3;
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assign attcode[7:4] = rfsh_dout_n3;
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assign attcode[3:0] = rfsh_dout_n2;
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assign attcode[3:0] = rfsh_dout_n2;
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assign chrcode[7:4] = rfsh_dout_n1;
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assign chrcode[7:4] = rfsh_dout_n1;
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assign chrcode[3:0] = rfsh_dout_n0;
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assign chrcode[3:0] = rfsh_dout_n0;
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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RAMB16_S4_S4 display_att_hi (
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RAMB16_S4_S4 display_att_hi (
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.DOA(rdwr_dout_n3), // Port A 4-bit Data Output
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.DOA(rdwr_dout_n3), // Port A 4-bit Data Output
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.DOB(rfsh_dout_n3), // Port B 4-bit Data Output
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.DOB(rfsh_dout_n3), // Port B 4-bit Data Output
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.CLKA(clk), // Port A Clock
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.CLKA(clk), // Port A Clock
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.CLKB(clk), // Port B Clock
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.CLKB(clk), // Port B Clock
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.DIA(rdwr_din_n3), // Port A 4-bit Data Input
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.DIA(rdwr_din_n3), // Port A 4-bit Data Input
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.DIB(rfsh_din_n3), // Port B 4-bit Data Input
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.DIB(rfsh_din_n3), // Port B 4-bit Data Input
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.ENA(en), // Port A RAM Enable Input
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.ENA(en), // Port A RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(wr), // Port A Write Enable Input
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.WEA(wr), // Port A Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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);
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);
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`include "dspatthi.init"
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`include "dspatthi.init"
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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RAMB16_S4_S4 display_att_lo (
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RAMB16_S4_S4 display_att_lo (
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.DOA(rdwr_dout_n2), // Port A 4-bit Data Output
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.DOA(rdwr_dout_n2), // Port A 4-bit Data Output
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.DOB(rfsh_dout_n2), // Port B 4-bit Data Output
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.DOB(rfsh_dout_n2), // Port B 4-bit Data Output
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.CLKA(clk), // Port A Clock
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.CLKA(clk), // Port A Clock
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.CLKB(clk), // Port B Clock
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.CLKB(clk), // Port B Clock
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.DIA(rdwr_din_n2), // Port A 4-bit Data Input
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.DIA(rdwr_din_n2), // Port A 4-bit Data Input
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.DIB(rfsh_din_n2), // Port B 4-bit Data Input
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.DIB(rfsh_din_n2), // Port B 4-bit Data Input
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.ENA(en), // Port A RAM Enable Input
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.ENA(en), // Port A RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(wr), // Port A Write Enable Input
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.WEA(wr), // Port A Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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);
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);
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`include "dspattlo.init"
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`include "dspattlo.init"
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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RAMB16_S4_S4 display_chr_hi (
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RAMB16_S4_S4 display_chr_hi (
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.DOA(rdwr_dout_n1), // Port A 4-bit Data Output
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.DOA(rdwr_dout_n1), // Port A 4-bit Data Output
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.DOB(rfsh_dout_n1), // Port B 4-bit Data Output
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.DOB(rfsh_dout_n1), // Port B 4-bit Data Output
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.CLKA(clk), // Port A Clock
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.CLKA(clk), // Port A Clock
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.CLKB(clk), // Port B Clock
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.CLKB(clk), // Port B Clock
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.DIA(rdwr_din_n1), // Port A 4-bit Data Input
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.DIA(rdwr_din_n1), // Port A 4-bit Data Input
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.DIB(rfsh_din_n1), // Port B 4-bit Data Input
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.DIB(rfsh_din_n1), // Port B 4-bit Data Input
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.ENA(en), // Port A RAM Enable Input
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.ENA(en), // Port A RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(wr), // Port A Write Enable Input
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.WEA(wr), // Port A Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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);
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);
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`include "dspchrhi.init"
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`include "dspchrhi.init"
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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// RAMB16_S4_S4: Spartan-3 4k x 4 Dual-Port RAM
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RAMB16_S4_S4 display_chr_lo (
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RAMB16_S4_S4 display_chr_lo (
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.DOA(rdwr_dout_n0), // Port A 4-bit Data Output
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.DOA(rdwr_dout_n0), // Port A 4-bit Data Output
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.DOB(rfsh_dout_n0), // Port B 4-bit Data Output
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.DOB(rfsh_dout_n0), // Port B 4-bit Data Output
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRA(rdwr_addr), // Port A 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.ADDRB(rfsh_addr), // Port B 12-bit Address Input
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.CLKA(clk), // Port A Clock
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.CLKA(clk), // Port A Clock
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.CLKB(clk), // Port B Clock
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.CLKB(clk), // Port B Clock
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.DIA(rdwr_din_n0), // Port A 4-bit Data Input
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.DIA(rdwr_din_n0), // Port A 4-bit Data Input
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.DIB(rfsh_din_n0), // Port B 4-bit Data Input
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.DIB(rfsh_din_n0), // Port B 4-bit Data Input
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.ENA(en), // Port A RAM Enable Input
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.ENA(en), // Port A RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.ENB(pixclk), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(wr), // Port A Write Enable Input
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.WEA(wr), // Port A Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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.WEB(1'b0) // Port B Write Enable Input
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);
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);
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`include "dspchrlo.init"
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`include "dspchrlo.init"
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (pixclk == 1) begin
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if (pixclk == 1) begin
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chrrow_out <= chrrow_in;
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chrrow_out <= chrrow_in;
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chrcol_out <= chrcol_in;
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chrcol_out <= chrcol_in;
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blank_out <= blank_in;
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blank_out <= blank_in;
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hsync_out <= hsync_in;
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hsync_out <= hsync_in;
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vsync_out <= vsync_in;
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vsync_out <= vsync_in;
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blink_out <= blink_in;
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blink_out <= blink_in;
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end
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end
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end
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end
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endmodule
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endmodule
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