;
|
;
|
; start.s -- startup and support routines
|
; start.s -- startup and support routines
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;
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;
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|
|
.set dmapaddr,0xC0000000 ; base of directly mapped addresses
|
.set dmapaddr,0xC0000000 ; base of directly mapped addresses
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.set stacktop,0xC0400000 ; monitor stack is at top of memory
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.set stacktop,0xC0400000 ; monitor stack is at top of memory
|
|
|
.set PSW,0 ; reg # of PSW
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.set PSW,0 ; reg # of PSW
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.set TLB_INDEX,1 ; reg # of TLB Index
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.set TLB_INDEX,1 ; reg # of TLB Index
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.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
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.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
|
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
|
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
|
.set TLB_ENTRIES,32 ; number of TLB entries
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.set TLB_ENTRIES,32 ; number of TLB entries
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.import _ecode
|
.import _ecode
|
.import _edata
|
.import _edata
|
.import _ebss
|
.import _ebss
|
|
|
.import serinit
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.import serinit
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.import ser0in
|
.import ser0in
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.import ser0out
|
.import ser0out
|
|
|
.import main
|
.import main
|
|
|
.export _bcode
|
.export _bcode
|
.export _bdata
|
.export _bdata
|
.export _bbss
|
.export _bbss
|
|
|
.export cin
|
.export cin
|
.export cout
|
.export cout
|
|
|
.export getTLB_HI
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.export getTLB_HI
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.export getTLB_LO
|
.export getTLB_LO
|
.export setTLB
|
.export setTLB
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.export wrtRndTLB
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.export wrtRndTLB
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.export probeTLB
|
.export probeTLB
|
.export wait
|
.export wait
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
_bcode:
|
_bcode:
|
|
|
.data
|
.data
|
_bdata:
|
_bdata:
|
|
|
.bss
|
.bss
|
_bbss:
|
_bbss:
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
reset:
|
reset:
|
j start
|
j start
|
|
|
interrupt:
|
interrupt:
|
j interrupt
|
j interrupt
|
|
|
userMiss:
|
userMiss:
|
j userMiss
|
j userMiss
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
cin:
|
cin:
|
j ser0in
|
j ser0in
|
|
|
cout:
|
cout:
|
j ser0out
|
j ser0out
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
start:
|
start:
|
; force CPU into a defined state
|
; force CPU into a defined state
|
mvts $0,PSW ; disable interrupts and user mode
|
mvts $0,PSW ; disable interrupts and user mode
|
|
|
; initialize TLB
|
; initialize TLB
|
mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries
|
mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries
|
add $8,$0,dmapaddr ; by impossible virtual page number
|
add $8,$0,dmapaddr ; by impossible virtual page number
|
add $9,$0,$0
|
add $9,$0,$0
|
add $10,$0,TLB_ENTRIES
|
add $10,$0,TLB_ENTRIES
|
tlbloop:
|
tlbloop:
|
mvts $8,TLB_ENTRY_HI
|
mvts $8,TLB_ENTRY_HI
|
mvts $9,TLB_INDEX
|
mvts $9,TLB_INDEX
|
tbwi
|
tbwi
|
add $8,$8,0x1000 ; all entries must be different
|
add $8,$8,0x1000 ; all entries must be different
|
add $9,$9,1
|
add $9,$9,1
|
bne $9,$10,tlbloop
|
bne $9,$10,tlbloop
|
|
|
; copy data segment
|
; copy data segment
|
add $10,$0,_bdata ; lowest dst addr to be written to
|
add $10,$0,_bdata ; lowest dst addr to be written to
|
add $8,$0,_edata ; one above the top dst addr
|
add $8,$0,_edata ; one above the top dst addr
|
sub $9,$8,$10 ; $9 = size of data segment
|
sub $9,$8,$10 ; $9 = size of data segment
|
add $9,$9,_ecode ; data is waiting right after code
|
add $9,$9,_ecode ; data is waiting right after code
|
j cpytest
|
j cpytest
|
cpyloop:
|
cpyloop:
|
ldw $11,$9,0 ; src addr in $9
|
ldw $11,$9,0 ; src addr in $9
|
stw $11,$8,0 ; dst addr in $8
|
stw $11,$8,0 ; dst addr in $8
|
cpytest:
|
cpytest:
|
sub $8,$8,4 ; downward
|
sub $8,$8,4 ; downward
|
sub $9,$9,4
|
sub $9,$9,4
|
bgeu $8,$10,cpyloop
|
bgeu $8,$10,cpyloop
|
|
|
; clear bss segment
|
; clear bss segment
|
add $8,$0,_bbss ; start with first word of bss
|
add $8,$0,_bbss ; start with first word of bss
|
add $9,$0,_ebss ; this is one above the top
|
add $9,$0,_ebss ; this is one above the top
|
j clrtest
|
j clrtest
|
clrloop:
|
clrloop:
|
stw $0,$8,0 ; dst addr in $8
|
stw $0,$8,0 ; dst addr in $8
|
add $8,$8,4 ; upward
|
add $8,$8,4 ; upward
|
clrtest:
|
clrtest:
|
bltu $8,$9,clrloop
|
bltu $8,$9,clrloop
|
|
|
; now do some useful work
|
; now do some useful work
|
add $29,$0,stacktop ; setup monitor stack
|
add $29,$0,stacktop ; setup monitor stack
|
jal serinit ; init serial interface
|
jal serinit ; init serial interface
|
jal main ; enter command loop
|
jal main ; enter command loop
|
|
|
; main should never return
|
; main should never return
|
j start ; just to be sure...
|
j start ; just to be sure...
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
; Word getTLB_HI(int index)
|
; Word getTLB_HI(int index)
|
getTLB_HI:
|
getTLB_HI:
|
mvts $4,TLB_INDEX
|
mvts $4,TLB_INDEX
|
tbri
|
tbri
|
mvfs $2,TLB_ENTRY_HI
|
mvfs $2,TLB_ENTRY_HI
|
jr $31
|
jr $31
|
|
|
; Word getTLB_LO(int index)
|
; Word getTLB_LO(int index)
|
getTLB_LO:
|
getTLB_LO:
|
mvts $4,TLB_INDEX
|
mvts $4,TLB_INDEX
|
tbri
|
tbri
|
mvfs $2,TLB_ENTRY_LO
|
mvfs $2,TLB_ENTRY_LO
|
jr $31
|
jr $31
|
|
|
; void setTLB(int index, Word entryHi, Word entryLo)
|
; void setTLB(int index, Word entryHi, Word entryLo)
|
setTLB:
|
setTLB:
|
mvts $4,TLB_INDEX
|
mvts $4,TLB_INDEX
|
mvts $5,TLB_ENTRY_HI
|
mvts $5,TLB_ENTRY_HI
|
mvts $6,TLB_ENTRY_LO
|
mvts $6,TLB_ENTRY_LO
|
tbwi
|
tbwi
|
jr $31
|
jr $31
|
|
|
; void wrtRndTLB(Word entryHi, Word entryLo)
|
; void wrtRndTLB(Word entryHi, Word entryLo)
|
wrtRndTLB:
|
wrtRndTLB:
|
mvts $4,TLB_ENTRY_HI
|
mvts $4,TLB_ENTRY_HI
|
mvts $5,TLB_ENTRY_LO
|
mvts $5,TLB_ENTRY_LO
|
tbwr
|
tbwr
|
jr $31
|
jr $31
|
|
|
; Word probeTLB(Word entryHi)
|
; Word probeTLB(Word entryHi)
|
probeTLB:
|
probeTLB:
|
mvts $4,TLB_ENTRY_HI
|
mvts $4,TLB_ENTRY_HI
|
tbs
|
tbs
|
mvfs $2,TLB_INDEX
|
mvfs $2,TLB_INDEX
|
jr $31
|
jr $31
|
|
|
; void wait(int n)
|
; void wait(int n)
|
wait:
|
wait:
|
j wait2
|
j wait2
|
wait1:
|
wait1:
|
add $4,$4,$0
|
add $4,$4,$0
|
sub $4,$4,1
|
sub $4,$4,1
|
wait2:
|
wait2:
|
bne $4,$0,wait1
|
bne $4,$0,wait1
|
jr $31
|
jr $31
|
|
|
