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Instruction Formats
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Instruction Formats
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-------------------
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-------------------
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RRR (three register operands)
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RRR (three register operands)
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RRS (two registers and a signed half operand)
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RRS (two registers and a signed half operand)
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RRH (two registers and an unsigned half operand)
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RRH (two registers and an unsigned half operand)
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RHH (one register and a half operand, high-order 16 bits encoded)
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RHH (one register and a half operand, high-order 16 bits encoded)
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RRB (two registers and a 16 bit signed offset operand)
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RRB (two registers and a 16 bit signed offset operand)
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J (no registers and a 26 bit signed offset operand)
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J (no registers and a 26 bit signed offset operand)
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JR (one register operand)
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JR (one register operand)
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Instruction Set
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Instruction Set
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---------------
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---------------
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Notation:
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Notation:
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'r[n]' The bits representing 'r' are padded with zeroes
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'r[n]' The bits representing 'r' are padded with zeroes
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to the left (or zeroes are dropped from the left)
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to the left (or zeroes are dropped from the left)
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until a width of n bits is reached.
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until a width of n bits is reached.
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'a || b' The bits representing 'a' and 'b' are concatenated;
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'a || b' The bits representing 'a' and 'b' are concatenated;
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'a' occupies the more significant bits.
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'a' occupies the more significant bits.
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All numbers are given in decimal (base 10), except when prefixed
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All numbers are given in decimal (base 10), except when prefixed
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with "0x", which means they are given in hexadecimal (base 16).
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with "0x", which means they are given in hexadecimal (base 16).
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ADD (add)
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ADD (add)
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format: RRR
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format: RRR
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coding: 0x00[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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coding: 0x00[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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assembler: add rd,rs1,rs2
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assembler: add rd,rs1,rs2
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example: add $1,$2,$3
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example: add $1,$2,$3
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operation: The contents of register rs2 are added to the contents
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operation: The contents of register rs2 are added to the contents
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of register rs1. The result is stored into register rd.
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of register rs1. The result is stored into register rd.
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Overflow is ignored.
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Overflow is ignored.
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ADDI (add immediate)
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ADDI (add immediate)
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format: RRS
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format: RRS
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coding: 0x01[6] || rs1[5] || rd[5] || simm[16]
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coding: 0x01[6] || rs1[5] || rd[5] || simm[16]
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assembler: add rd,rs1,simm
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assembler: add rd,rs1,simm
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example: add $1,$2,1234
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example: add $1,$2,1234
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operation: The sign-extended immediate constant simm is added to
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operation: The sign-extended immediate constant simm is added to
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the contents of register rs1. The result is stored into
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the contents of register rs1. The result is stored into
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register rd. Overflow is ignored.
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register rd. Overflow is ignored.
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SUB (subtract)
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SUB (subtract)
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format: RRR
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format: RRR
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coding: 0x02[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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coding: 0x02[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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assembler: sub rd,rs1,rs2
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assembler: sub rd,rs1,rs2
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example: sub $1,$2,$3
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example: sub $1,$2,$3
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operation: The contents of register rs2 are subtracted from the
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operation: The contents of register rs2 are subtracted from the
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contents of register rs1. The result is stored into
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contents of register rs1. The result is stored into
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register rd. Overflow is ignored.
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register rd. Overflow is ignored.
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SUBI (subtract immediate)
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SUBI (subtract immediate)
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format: RRS
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format: RRS
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coding: 0x03[6] || rs1[5] || rd[5] || simm[16]
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coding: 0x03[6] || rs1[5] || rd[5] || simm[16]
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assembler: sub rd,rs1,simm
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assembler: sub rd,rs1,simm
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example: add $1,$2,1234
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example: add $1,$2,1234
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operation: The sign-extended immediate constant simm is subtracted
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operation: The sign-extended immediate constant simm is subtracted
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from the contents of register rs1. The result is stored
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from the contents of register rs1. The result is stored
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into register rd. Overflow is ignored.
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into register rd. Overflow is ignored.
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AND (logical and)
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AND (logical and)
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format: RRR
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format: RRR
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coding: 0x10[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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coding: 0x10[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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assembler: and rd,rs1,rs2
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assembler: and rd,rs1,rs2
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example: and $1,$2,$3
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example: and $1,$2,$3
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operation: The contents of register rs2 are bitwise anded with the
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operation: The contents of register rs2 are bitwise anded with the
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contents of register rs1. The result is stored into
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contents of register rs1. The result is stored into
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register rd.
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register rd.
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ANDI (logical and immediate)
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ANDI (logical and immediate)
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format: RRH
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format: RRH
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coding: 0x11[6] || rs1[5] || rd[5] || uimm[16]
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coding: 0x11[6] || rs1[5] || rd[5] || uimm[16]
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assembler: and rd,rs1,uimm
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assembler: and rd,rs1,uimm
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example: and $1,$2,1234
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example: and $1,$2,1234
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operation: The zero-extended immediate constant uimm is bitwise
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operation: The zero-extended immediate constant uimm is bitwise
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anded with the contents of register rs1. The result
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anded with the contents of register rs1. The result
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is stored into register rd.
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is stored into register rd.
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OR (logical or)
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OR (logical or)
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format: RRR
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format: RRR
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coding: 0x12[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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coding: 0x12[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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assembler: or rd,rs1,rs2
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assembler: or rd,rs1,rs2
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example: or $1,$2,$3
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example: or $1,$2,$3
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operation: The contents of register rs2 are bitwise ored with the
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operation: The contents of register rs2 are bitwise ored with the
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contents of register rs1. The result is stored into
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contents of register rs1. The result is stored into
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register rd.
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register rd.
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ORI (logical or immediate)
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ORI (logical or immediate)
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format: RRH
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format: RRH
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coding: 0x13[6] || rs1[5] || rd[5] || uimm[16]
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coding: 0x13[6] || rs1[5] || rd[5] || uimm[16]
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assembler: or rd,rs1,uimm
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assembler: or rd,rs1,uimm
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example: or $1,$2,1234
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example: or $1,$2,1234
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operation: The zero-extended immediate constant uimm is bitwise
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operation: The zero-extended immediate constant uimm is bitwise
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ored with the contents of register rs1. The result
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ored with the contents of register rs1. The result
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is stored into register rd.
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is stored into register rd.
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XOR (logical xor)
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XOR (logical xor)
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format: RRR
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format: RRR
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coding: 0x14[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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coding: 0x14[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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assembler: xor rd,rs1,rs2
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assembler: xor rd,rs1,rs2
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example: xor $1,$2,$3
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example: xor $1,$2,$3
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operation: The contents of register rs2 are bitwise xored with the
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operation: The contents of register rs2 are bitwise xored with the
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contents of register rs1. The result is stored into
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contents of register rs1. The result is stored into
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register rd.
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register rd.
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Remark: (a xor b) <=> ((a and ~b) or (~a and b))
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Remark: (a xor b) <=> ((a and ~b) or (~a and b))
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XORI (logical xor immediate)
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XORI (logical xor immediate)
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format: RRH
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format: RRH
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coding: 0x15[6] || rs1[5] || rd[5] || uimm[16]
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coding: 0x15[6] || rs1[5] || rd[5] || uimm[16]
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assembler: xor rd,rs1,uimm
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assembler: xor rd,rs1,uimm
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example: xor $1,$2,1234
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example: xor $1,$2,1234
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operation: The zero-extended immediate constant uimm is bitwise
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operation: The zero-extended immediate constant uimm is bitwise
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xored with the contents of register rs1. The result
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xored with the contents of register rs1. The result
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is stored into register rd.
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is stored into register rd.
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Remark: (a xor b) <=> ((a and ~b) or (~a and b))
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Remark: (a xor b) <=> ((a and ~b) or (~a and b))
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XNOR (logical xnor)
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XNOR (logical xnor)
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format: RRR
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format: RRR
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coding: 0x16[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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coding: 0x16[6] || rs1[5] || rs2[5] || rd[5] || 0[11]
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assembler: xnor rd,rs1,rs2
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assembler: xnor rd,rs1,rs2
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example: xnor $1,$2,$3
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example: xnor $1,$2,$3
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operation: The contents of register rs2 are bitwise xnored with the
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operation: The contents of register rs2 are bitwise xnored with the
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contents of register rs1. The result is stored into
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contents of register rs1. The result is stored into
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register rd.
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register rd.
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Remark: (a xnor b) <=> ((a and b) or (~a and ~b))
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Remark: (a xnor b) <=> ((a and b) or (~a and ~b))
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XNORI (logical xnor immediate)
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XNORI (logical xnor immediate)
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format: RRH
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format: RRH
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coding: 0x17[6] || rs1[5] || rd[5] || uimm[16]
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coding: 0x17[6] || rs1[5] || rd[5] || uimm[16]
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assembler: xnor rd,rs1,uimm
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assembler: xnor rd,rs1,uimm
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example: xnor $1,$2,1234
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example: xnor $1,$2,1234
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operation: The zero-extended immediate constant uimm is bitwise
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operation: The zero-extended immediate constant uimm is bitwise
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xnored with the contents of register rs1. The result
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xnored with the contents of register rs1. The result
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is stored into register rd.
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is stored into register rd.
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Remark: (a xnor b) <=> ((a and b) or (~a and ~b))
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Remark: (a xnor b) <=> ((a and b) or (~a and ~b))
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LDHI (load high immediate)
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LDHI (load high immediate)
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format: RHH
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format: RHH
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coding: 0x1F[6] || 0[5] || rd[5] || uimm[16]
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coding: 0x1F[6] || 0[5] || rd[5] || uimm[16]
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assembler: ldhi rd,uimm
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assembler: ldhi rd,uimm
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example: ldhi $1,1234
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example: ldhi $1,1234
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operation: The zero-extended immediate constant uimm is shifted
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operation: The zero-extended immediate constant uimm is shifted
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left by 16 bits. The result is stored into register rd.
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left by 16 bits. The result is stored into register rd.
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BEQ (branch on equal)
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BEQ (branch on equal)
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format: RRB
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format: RRB
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coding: 0x20[6] || rs1[5] || rs2[5] || simm[16]
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coding: 0x20[6] || rs1[5] || rs2[5] || simm[16]
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assembler: beq rs1,rs2,target
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assembler: beq rs1,rs2,target
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example: beq $1,$2,label3
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example: beq $1,$2,label3
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operation: If the contents of register rs1 are equal to the contents
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operation: If the contents of register rs1 are equal to the contents
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of register rs2, the sign-extended immediate constant
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of register rs2, the sign-extended immediate constant
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simm is shifted left by two bits and added to the address
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simm is shifted left by two bits and added to the address
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of the instruction following the branch instruction. The
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of the instruction following the branch instruction. The
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result is placed into the program counter. If the contents
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result is placed into the program counter. If the contents
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differ, the next instruction after the branch is executed.
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differ, the next instruction after the branch is executed.
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BNE (branch on not equal)
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BNE (branch on not equal)
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format: RRB
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format: RRB
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coding: 0x21[6] || rs1[5] || rs2[5] || simm[16]
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coding: 0x21[6] || rs1[5] || rs2[5] || simm[16]
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assembler: bne rs1,rs2,target
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assembler: bne rs1,rs2,target
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example: bne $1,$2,label3
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example: bne $1,$2,label3
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operation: If the contents of register rs1 are not equal to the contents
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operation: If the contents of register rs1 are not equal to the contents
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of register rs2, the sign-extended immediate constant
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of register rs2, the sign-extended immediate constant
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simm is shifted left by two bits and added to the address
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simm is shifted left by two bits and added to the address
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of the instruction following the branch instruction. The
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of the instruction following the branch instruction. The
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result is placed into the program counter. If the contents
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result is placed into the program counter. If the contents
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are equal, the next instruction after the branch is executed.
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are equal, the next instruction after the branch is executed.
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BLEU (branch on less or equal unsigned)
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BLEU (branch on less or equal unsigned)
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format: RRB
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format: RRB
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coding: 0x23[6] || rs1[5] || rs2[5] || simm[16]
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coding: 0x23[6] || rs1[5] || rs2[5] || simm[16]
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assembler: bleu rs1,rs2,target
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assembler: bleu rs1,rs2,target
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example: bleu $1,$2,label3
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example: bleu $1,$2,label3
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operation: If the contents of register rs1 are less than or equal
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operation: If the contents of register rs1 are less than or equal
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to the contents of register rs2 (both are interpreted as
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to the contents of register rs2 (both are interpreted as
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unsigned numbers), the sign-extended immediate constant
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unsigned numbers), the sign-extended immediate constant
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simm is shifted left by two bits and added to the address
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simm is shifted left by two bits and added to the address
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of the instruction following the branch instruction. The
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of the instruction following the branch instruction. The
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result is placed into the program counter. If the contents
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result is placed into the program counter. If the contents
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do not satisfy the condition, the next instruction after
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do not satisfy the condition, the next instruction after
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the branch is executed.
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the branch is executed.
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BLTU (branch on less than unsigned)
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BLTU (branch on less than unsigned)
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format: RRB
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format: RRB
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coding: 0x25[6] || rs1[5] || rs2[5] || simm[16]
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coding: 0x25[6] || rs1[5] || rs2[5] || simm[16]
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assembler: bltu rs1,rs2,target
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assembler: bltu rs1,rs2,target
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example: bltu $1,$2,label3
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example: bltu $1,$2,label3
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operation: If the contents of register rs1 are less than the contents
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operation: If the contents of register rs1 are less than the contents
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of register rs2 (both are interpreted as unsigned numbers),
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of register rs2 (both are interpreted as unsigned numbers),
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the sign-extended immediate constant simm is shifted left
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the sign-extended immediate constant simm is shifted left
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by two bits and added to the address of the instruction
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by two bits and added to the address of the instruction
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following the branch instruction. The result is placed into
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following the branch instruction. The result is placed into
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the program counter. If the contents do not satisfy the
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the program counter. If the contents do not satisfy the
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condition, the next instruction after the branch is executed.
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condition, the next instruction after the branch is executed.
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BGEU (branch on greater or equal unsigned)
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BGEU (branch on greater or equal unsigned)
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format: RRB
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format: RRB
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coding: 0x27[6] || rs1[5] || rs2[5] || simm[16]
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coding: 0x27[6] || rs1[5] || rs2[5] || simm[16]
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assembler: bgeu rs1,rs2,target
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assembler: bgeu rs1,rs2,target
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example: bgeu $1,$2,label3
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example: bgeu $1,$2,label3
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operation: If the contents of register rs1 are greater than or equal
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operation: If the contents of register rs1 are greater than or equal
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to the contents of register rs2 (both are interpreted as
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to the contents of register rs2 (both are interpreted as
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unsigned numbers), the sign-extended immediate constant
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unsigned numbers), the sign-extended immediate constant
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simm is shifted left by two bits and added to the address
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simm is shifted left by two bits and added to the address
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of the instruction following the branch instruction. The
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of the instruction following the branch instruction. The
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result is placed into the program counter. If the contents
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result is placed into the program counter. If the contents
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do not satisfy the condition, the next instruction after
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do not satisfy the condition, the next instruction after
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the branch is executed.
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the branch is executed.
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BGTU (branch on greater than unsigned)
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BGTU (branch on greater than unsigned)
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format: RRB
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format: RRB
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coding: 0x29[6] || rs1[5] || rs2[5] || simm[16]
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coding: 0x29[6] || rs1[5] || rs2[5] || simm[16]
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assembler: bgtu rs1,rs2,target
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assembler: bgtu rs1,rs2,target
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example: bgtu $1,$2,label3
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example: bgtu $1,$2,label3
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operation: If the contents of register rs1 are greater than the contents
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operation: If the contents of register rs1 are greater than the contents
|
of register rs2 (both are interpreted as unsigned numbers),
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of register rs2 (both are interpreted as unsigned numbers),
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the sign-extended immediate constant simm is shifted left
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the sign-extended immediate constant simm is shifted left
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by two bits and added to the address of the instruction
|
by two bits and added to the address of the instruction
|
following the branch instruction. The result is placed into
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following the branch instruction. The result is placed into
|
the program counter. If the contents do not satisfy the
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the program counter. If the contents do not satisfy the
|
condition, the next instruction after the branch is executed.
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condition, the next instruction after the branch is executed.
|
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J (jump)
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J (jump)
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format: J
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format: J
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coding: 0x2A[6] || simm[26]
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coding: 0x2A[6] || simm[26]
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assembler: j target
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assembler: j target
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example: j label3
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example: j label3
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operation: The sign-extended immediate constant simm is shifted left
|
operation: The sign-extended immediate constant simm is shifted left
|
by two bits and added to the address of the instruction
|
by two bits and added to the address of the instruction
|
following the jump instruction. The result is placed into
|
following the jump instruction. The result is placed into
|
the program counter.
|
the program counter.
|
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JR (jump register)
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JR (jump register)
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format: JR
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format: JR
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coding: 0x2B[6] || rs[5] || 0[5] || 0[16]
|
coding: 0x2B[6] || rs[5] || 0[5] || 0[16]
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assembler: jr rs
|
assembler: jr rs
|
example: jr $31
|
example: jr $31
|
operation: The contents of register rs are placed into the program
|
operation: The contents of register rs are placed into the program
|
counter.
|
counter.
|
|
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JAL (jump and link)
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JAL (jump and link)
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format: J
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format: J
|
coding: 0x2C[6] || simm[26]
|
coding: 0x2C[6] || simm[26]
|
assembler: jal target
|
assembler: jal target
|
example: jal label3
|
example: jal label3
|
operation: The address of the instruction following the jal instruction
|
operation: The address of the instruction following the jal instruction
|
is placed into register 31. The sign-extended immediate
|
is placed into register 31. The sign-extended immediate
|
constant simm is shifted left by two bits and added to the
|
constant simm is shifted left by two bits and added to the
|
address of the instruction following the jal instruction.
|
address of the instruction following the jal instruction.
|
The result is placed into the program counter.
|
The result is placed into the program counter.
|
|
|
LDW (load word)
|
LDW (load word)
|
format: RRS
|
format: RRS
|
coding: 0x30[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x30[6] || rs[5] || rd[5] || simm[16]
|
assembler: ldw rd,rs,simm
|
assembler: ldw rd,rs,simm
|
example: ldw $1,$2,1234
|
example: ldw $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
A word is read from this address and stored into register
|
A word is read from this address and stored into register
|
rd.
|
rd.
|
|
|
LDH (load halfword)
|
LDH (load halfword)
|
format: RRS
|
format: RRS
|
coding: 0x31[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x31[6] || rs[5] || rd[5] || simm[16]
|
assembler: ldh rd,rs,simm
|
assembler: ldh rd,rs,simm
|
example: ldh $1,$2,1234
|
example: ldh $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
A halfword is read from this address, sign-extended, and
|
A halfword is read from this address, sign-extended, and
|
stored into register rd.
|
stored into register rd.
|
|
|
LDHU (load halfword unsigned)
|
LDHU (load halfword unsigned)
|
format: RRS
|
format: RRS
|
coding: 0x32[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x32[6] || rs[5] || rd[5] || simm[16]
|
assembler: ldhu rd,rs,simm
|
assembler: ldhu rd,rs,simm
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example: ldhu $1,$2,1234
|
example: ldhu $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
A halfword is read from this address, zero-extended, and
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A halfword is read from this address, zero-extended, and
|
stored into register rd.
|
stored into register rd.
|
|
|
LDB (load byte)
|
LDB (load byte)
|
format: RRS
|
format: RRS
|
coding: 0x33[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x33[6] || rs[5] || rd[5] || simm[16]
|
assembler: ldb rd,rs,simm
|
assembler: ldb rd,rs,simm
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example: ldb $1,$2,1234
|
example: ldb $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
A byte is read from this address, sign-extended, and stored
|
A byte is read from this address, sign-extended, and stored
|
into register rd.
|
into register rd.
|
|
|
LDBU (load byte unsigned)
|
LDBU (load byte unsigned)
|
format: RRS
|
format: RRS
|
coding: 0x34[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x34[6] || rs[5] || rd[5] || simm[16]
|
assembler: ldbu rd,rs,simm
|
assembler: ldbu rd,rs,simm
|
example: ldbu $1,$2,1234
|
example: ldbu $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
A byte is read from this address, zero-extended, and stored
|
A byte is read from this address, zero-extended, and stored
|
into register rd.
|
into register rd.
|
|
|
STW (store word)
|
STW (store word)
|
format: RRS
|
format: RRS
|
coding: 0x35[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x35[6] || rs[5] || rd[5] || simm[16]
|
assembler: stw rd,rs,simm
|
assembler: stw rd,rs,simm
|
example: stw $1,$2,1234
|
example: stw $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
The contents of register rd (all 32 bits) are stored
|
The contents of register rd (all 32 bits) are stored
|
as a word to this address.
|
as a word to this address.
|
|
|
STH (store halfword)
|
STH (store halfword)
|
format: RRS
|
format: RRS
|
coding: 0x36[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x36[6] || rs[5] || rd[5] || simm[16]
|
assembler: sth rd,rs,simm
|
assembler: sth rd,rs,simm
|
example: sth $1,$2,1234
|
example: sth $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
The contents of register rd (the lower 16 bits) are stored
|
The contents of register rd (the lower 16 bits) are stored
|
as a halfword to this address.
|
as a halfword to this address.
|
|
|
STB (store byte)
|
STB (store byte)
|
format: RRS
|
format: RRS
|
coding: 0x37[6] || rs[5] || rd[5] || simm[16]
|
coding: 0x37[6] || rs[5] || rd[5] || simm[16]
|
assembler: stb rd,rs,simm
|
assembler: stb rd,rs,simm
|
example: stb $1,$2,1234
|
example: stb $1,$2,1234
|
operation: The sign-extended immediate constant simm is added to the
|
operation: The sign-extended immediate constant simm is added to the
|
contents of register rs to form an effective memory address.
|
contents of register rs to form an effective memory address.
|
The contents of register rd (the lowest 8 bits) are stored
|
The contents of register rd (the lowest 8 bits) are stored
|
as a byte to this address.
|
as a byte to this address.
|
|
|
|
|
Interrupts and Exceptions
|
Interrupts and Exceptions
|
-------------------------
|
-------------------------
|
|
|
There are neither interrupts nor exceptions in this version of ECO32e.
|
There are neither interrupts nor exceptions in this version of ECO32e.
|
Unknown opcodes should nevertheless be recognized. A CPU simulation can
|
Unknown opcodes should nevertheless be recognized. A CPU simulation can
|
then report the execution of an unknown opcode; an implementation may
|
then report the execution of an unknown opcode; an implementation may
|
trap such an execution in a state of its controller which cannot be left
|
trap such an execution in a state of its controller which cannot be left
|
without reset.
|
without reset.
|
|
|
|
|
Peripherals
|
Peripherals
|
-----------
|
-----------
|
|
|
Peripherals are memory-mapped. They need only support word accesses.
|
Peripherals are memory-mapped. They need only support word accesses.
|
A sensible reaction to accesses with smaller widths (halfword or byte)
|
A sensible reaction to accesses with smaller widths (halfword or byte)
|
is not required.
|
is not required.
|
|
|
In this version of ECO32e there are only two peripherals: a character
|
In this version of ECO32e there are only two peripherals: a character
|
display and a keyboard.
|
display and a keyboard.
|
|
|
The character display is capable of showing 30 lines with 80 characters
|
The character display is capable of showing 30 lines with 80 characters
|
each. Its base address is 0x30100000. Each line occupies 128 words in
|
each. Its base address is 0x30100000. Each line occupies 128 words in
|
the I/O address space, one word for each column (and 48 unusable columns
|
the I/O address space, one word for each column (and 48 unusable columns
|
at the end of the line). Therefore the address to which a character is
|
at the end of the line). Therefore the address to which a character is
|
written and its location on the screen are related as follows:
|
written and its location on the screen are related as follows:
|
address = 0x30100000 + (line * 128 + column) * 4
|
address = 0x30100000 + (line * 128 + column) * 4
|
The character to be displayed must be written as a word to the corresponding
|
The character to be displayed must be written as a word to the corresponding
|
address with its ASCII code contained in the lowest 8 bits of the word.
|
address with its ASCII code contained in the lowest 8 bits of the word.
|
|
|
The keyboard is represented by two I/O registers. The status register
|
The keyboard is represented by two I/O registers. The status register
|
is located at address 0x30200000. When read (32 bits), its LSB indicates
|
is located at address 0x30200000. When read (32 bits), its LSB indicates
|
if a character has been received from the physical keyboard. If this bit
|
if a character has been received from the physical keyboard. If this bit
|
is 1, the character can be read at address 0x30200004, the address of
|
is 1, the character can be read at address 0x30200004, the address of
|
the data register. By reading this latter address, the LSB of the
|
the data register. By reading this latter address, the LSB of the
|
status register is automatically reset to 0. The data register must be
|
status register is automatically reset to 0. The data register must be
|
read with a word read; the character read is contained in the lowest
|
read with a word read; the character read is contained in the lowest
|
8 bits of the word.
|
8 bits of the word.
|
|
|
|
|
