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FPGA Implementations of ECO32
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FPGA Implementations of ECO32
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=============================
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=============================
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eco32-00
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eco32-00
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--------
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--------
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This is essentially the same as the solution of assigment 9 of the
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This is essentially the same as the solution of assigment 9 of the
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course "Hardware for Embedded Systems", i.e., an implementation of
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course "Hardware for Embedded Systems", i.e., an implementation of
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ECO32e. The differences are:
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ECO32e. The differences are:
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a) The reset circuit is moved to a subdirectory of its own. The
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a) The reset circuit is moved to a subdirectory of its own. The
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duration of the reset pulse is reduced to 2^24/50MHz = 0.3 sec,
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duration of the reset pulse is reduced to 2^24/50MHz = 0.3 sec,
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a quarter of the original duration.
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a quarter of the original duration.
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b) The reset circuit is connected to the pushbutton on the carrier
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b) The reset circuit is connected to the pushbutton on the carrier
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board, which has been designated for reset by the manufacturer.
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board, which has been designated for reset by the manufacturer.
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c) The bus controller is moved to a subdirectory of its own.
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c) The bus controller is moved to a subdirectory of its own.
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d) The top-level description is transformed from a schematic into
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d) The top-level description is transformed from a schematic into
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plain text. This in turn eliminates the need for top-level
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plain text. This in turn eliminates the need for top-level
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symbols of the Reset/ROM/RAM/Busctrl/CPU/DSP/KBD circuits.
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symbols of the Reset/ROM/RAM/Busctrl/CPU/DSP/KBD circuits.
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eco32-01
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eco32-01
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--------
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--------
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We have a new module, "ser", which represents the circuit for a
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We have a new module, "ser", which represents the circuit for a
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serial interface (8 bit data, no parity, 1 stop bit, 38400 baud).
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serial interface (8 bit data, no parity, 1 stop bit, 38400 baud).
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The data is buffered twice in both directions. The module is
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The data is buffered twice in both directions. The module is
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instanciated once; the data in/out lines are connected to the
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instanciated once; the data in/out lines are connected to the
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RS232 interface on the carrier board. The bus controller got
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RS232 interface on the carrier board. The bus controller got
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the necessary additional connections to drive the module.
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the necessary additional connections to drive the module.
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eco32-02
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eco32-02
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--------
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--------
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The fake RAM module is replaced by a preliminary implementation of
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The fake RAM module is replaced by a preliminary implementation of
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real RAM. It uses the block RAM of the FPGA (instead of the SDRAM
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real RAM. It uses the block RAM of the FPGA (instead of the SDRAM
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mounted as an extra chip on the board that the final implementation
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mounted as an extra chip on the board that the final implementation
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will use). It is therefore very small in size: 4 blocks of 16K bits
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will use). It is therefore very small in size: 4 blocks of 16K bits
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each yield a total size of 2 KWords (8K bytes).
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each yield a total size of 2 KWords (8K bytes).
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eco32-03
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eco32-03
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--------
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--------
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This revision corrects an error which should have been corrected
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This revision corrects an error which should have been corrected
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a long time ago: the instructions ldb and ldh never sign-extended
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a long time ago: the instructions ldb and ldh never sign-extended
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their loaded data. On top of that, the instructions ldbu and ldhu
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their loaded data. On top of that, the instructions ldbu and ldhu
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never placed zeroes into the bit positions 31 to 8 and 31 to 16,
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never placed zeroes into the bit positions 31 to 8 and 31 to 16,
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respectively. This went undetected so far, because the implementation
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respectively. This went undetected so far, because the implementation
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of the bus did this already, although it is not explicitly requested.
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of the bus did this already, although it is not explicitly requested.
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eco32-04
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eco32-04
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--------
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--------
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This version got a shift unit. It is connected in parallel to the
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This version got a shift unit. It is connected in parallel to the
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ALU, feeding its output into an expanded multiplexer. Because
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ALU, feeding its output into an expanded multiplexer. Because
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arithmetic right shifts are slow, shifting needs an extra cycle
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arithmetic right shifts are slow, shifting needs an extra cycle
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to complete. Even then it was necessary to request the place and
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to complete. Even then it was necessary to request the place and
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route effort level "high" to get by with a clock period of 20 nsec.
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route effort level "high" to get by with a clock period of 20 nsec.
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eco32-05
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eco32-05
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--------
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--------
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Again there was an error to correct: I tried to scroll the display
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Again there was an error to correct: I tried to scroll the display
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by copying the display memory contents and discovered that reading
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by copying the display memory contents and discovered that reading
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the memory needs an additional bus cycle (because the memory is
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the memory needs an additional bus cycle (because the memory is
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clocked). A simple state machine had to be written, which in turn
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clocked). A simple state machine had to be written, which in turn
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needed the reset signal. I changed the top-level description of
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needed the reset signal. I changed the top-level description of
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the display from a schematic to plain text.
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the display from a schematic to plain text.
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eco32-06
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eco32-06
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--------
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--------
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An easy job: I implemented the "jalr" instruction.
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An easy job: I implemented the "jalr" instruction.
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eco32-07
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eco32-07
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--------
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--------
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This is the first step in getting the real memory to work:
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This is the first step in getting the real memory to work:
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I integrated the clock/reset module from my SDRAM controller
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I integrated the clock/reset module from my SDRAM controller
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experiments. I also corrected the naming of the flash ROM
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experiments. I also corrected the naming of the flash ROM
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signals; all active-low signals are now consistently named
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signals; all active-low signals are now consistently named
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with a trailing "_n".
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with a trailing "_n".
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eco32-08
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eco32-08
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--------
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--------
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We now have a working SDRAM controller!
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We now have a working SDRAM controller!
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eco32-09
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eco32-09
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--------
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--------
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Second serial interface added.
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Second serial interface added.
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eco32-10
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eco32-10
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--------
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--------
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Branches based on signed comparisons added.
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Branches based on signed comparisons added.
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eco32-11
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eco32-11
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--------
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--------
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Timer added.
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Timer added.
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eco32-12
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eco32-12
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--------
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--------
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Multiply, divide, and remainder instructions done.
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Multiply, divide, and remainder instructions done.
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eco32-13
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eco32-13
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--------
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--------
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A first attempt to introduce virtual addressing: a totally
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A first attempt to introduce virtual addressing: a totally
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minimalistic MMU consisting of two AND gates which suppress
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minimalistic MMU consisting of two AND gates which suppress
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the two MSBs of the virtual address if they are set. If
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the two MSBs of the virtual address if they are set. If
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they are not, too bad - the virtual address is then mapped
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they are not, too bad - the virtual address is then mapped
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to physical address 0.
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to physical address 0.
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eco32-14
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eco32-14
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--------
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--------
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A couple of steps to make interrupts available:
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A couple of steps to make interrupts available:
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a) The CPU gets an input vector of 16 interrupt request lines which
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a) The CPU gets an input vector of 16 interrupt request lines which
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are all tied to 0 in the top-level design external to the CPU.
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are all tied to 0 in the top-level design external to the CPU.
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b) The timer circuit's control register gets an interrupt enable bit,
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b) The timer circuit's control register gets an interrupt enable bit,
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which gates the 'timer expired' status bit onto an additional
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which gates the 'timer expired' status bit onto an additional
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output line, the timer's interrupt request line. This line is
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output line, the timer's interrupt request line. This line is
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connected to the CPU's irq line 14.
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connected to the CPU's irq line 14.
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c) Inside the CPU there must be a set of 4 special registers. They
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c) Inside the CPU there must be a set of 4 special registers. They
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are implemented in a separate module. Two instructions (mvfs and
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are implemented in a separate module. Two instructions (mvfs and
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mvts) transfer data between the standard and the special register
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mvts) transfer data between the standard and the special register
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sets. The data input of the special register set is connected to
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sets. The data input of the special register set is connected to
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the standard register data output 2; the write enable signal for
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the standard register data output 2; the write enable signal for
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the special register set is controlled by the CPU's state machine.
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the special register set is controlled by the CPU's state machine.
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The data output of the special register set is connected to the
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The data output of the special register set is connected to the
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data input 2 multiplexer of the standard register set, which has
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data input 2 multiplexer of the standard register set, which has
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to be widened by one input (and by one control line also). The
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to be widened by one input (and by one control line also). The
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register number which selects the special register from/to which
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register number which selects the special register from/to which
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reading/writing should take place comes from the instruction
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reading/writing should take place comes from the instruction
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register's immediate constant. The two new instructions get one
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register's immediate constant. The two new instructions get one
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extra state each in the CPU's state machine.
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extra state each in the CPU's state machine.
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d) For interrupts and exceptions to take place there must be four
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d) For interrupts and exceptions to take place there must be four
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additional values available which can be loaded into the PC:
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additional values available which can be loaded into the PC:
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0xE0000004 general interrupts (V-bit of the PSW off)
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0xE0000004 general interrupts (V-bit of the PSW off)
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0xC0000004 general interrupts (V-bit of the PSW on)
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0xC0000004 general interrupts (V-bit of the PSW on)
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0xE0000008 user TLB miss (V-bit of the PSW off)
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0xE0000008 user TLB miss (V-bit of the PSW off)
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0xC0000008 user TLB miss (V-bit of the PSW on)
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0xC0000008 user TLB miss (V-bit of the PSW on)
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The contents of the special register 0 (the PSW) are needed at
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The contents of the special register 0 (the PSW) are needed at
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several places in the description of the CPU's state machine.
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several places in the description of the CPU's state machine.
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They have to be set also, independently of the mvts instruction.
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They have to be set also, independently of the mvts instruction.
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Therefore an extra data path from/to the special register set
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Therefore an extra data path from/to the special register set
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is established, together with a separate write signal for the
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is established, together with a separate write signal for the
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PSW. The state machine gets two new states, one to acknowledge
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PSW. The state machine gets two new states, one to acknowledge
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interrupts and another one to implement the rfx instruction.
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interrupts and another one to implement the rfx instruction.
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Each instruction tests a specific 'interrupt trigger line'
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Each instruction tests a specific 'interrupt trigger line'
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before returning to state 1 (instruction fetch). If it is set,
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before returning to state 1 (instruction fetch). If it is set,
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the state machine branches to the 'interrupt' state. In this
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the state machine branches to the 'interrupt' state. In this
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way we don't need a separate state before the 'instruction
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way we don't need a separate state before the 'instruction
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fetch' state to check for interrupts (and also avoid the
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fetch' state to check for interrupts (and also avoid the
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unpleasant alternative: to merge interrupt detection into
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unpleasant alternative: to merge interrupt detection into
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the fetch state - think of the already-incremented pc, for
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the fetch state - think of the already-incremented pc, for
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example). The trigger signal is set if there is any interrupt
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example). The trigger signal is set if there is any interrupt
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request present, its mask is open, and the global interrupt
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request present, its mask is open, and the global interrupt
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enable (in the PSW) is set. The ECO32 architecture defines
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enable (in the PSW) is set. The ECO32 architecture defines
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5 bits in the PSW to be the priority of the last acknowledged
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5 bits in the PSW to be the priority of the last acknowledged
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interrupt. Therefore a priority encoder takes the vector of
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interrupt. Therefore a priority encoder takes the vector of
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interrupt requests (possibly modified by closed mask bits)
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interrupt requests (possibly modified by closed mask bits)
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and determines the highest unmasked interrupt from that. The
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and determines the highest unmasked interrupt from that. The
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two additional states in the state machine also handle the
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two additional states in the state machine also handle the
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two stacks (each three positions deep) for the 'interrupt
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two stacks (each three positions deep) for the 'interrupt
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enable' and 'user mode' flags within the PSW.
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enable' and 'user mode' flags within the PSW.
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e) Since its construction, the ALU had two unused function encodings;
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e) Since its construction, the ALU had two unused function encodings;
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they had been assigned to add and subtract, but were never used.
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they had been assigned to add and subtract, but were never used.
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They now deliver either the first or the second operand of the ALU
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They now deliver either the first or the second operand of the ALU
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to the output, unchanged. This simplifies three instructions (ldhi,
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to the output, unchanged. This simplifies three instructions (ldhi,
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jr, rfx) as well as the interrupt state in the CPU's state machine.
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jr, rfx) as well as the interrupt state in the CPU's state machine.
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eco32-15
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eco32-15
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--------
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--------
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We now have the 'trap' instruction. This is an important first
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We now have the 'trap' instruction. This is an important first
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example of an exception.
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example of an exception.
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eco32-16
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eco32-16
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--------
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--------
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This version accepts the four TLB instructions as valid instructions
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This version accepts the four TLB instructions as valid instructions
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(but treats them as no-ops).
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(but treats them as no-ops).
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eco32-17
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eco32-17
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--------
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--------
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A couple of steps to make exceptions work:
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A couple of steps to make exceptions work:
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a) There are only 16 interrupts, so irq_priority is only [3:0] wide.
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a) There are only 16 interrupts, so irq_priority is only [3:0] wide.
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The leading bit of the interrupt/exception priority in the PSW is
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The leading bit of the interrupt/exception priority in the PSW is
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explicitly set to 0 in state 15 (interrupt).
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explicitly set to 0 in state 15 (interrupt).
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b) Generally, states returning to state 1 (instruction fetch) check
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b) Generally, states returning to state 1 (instruction fetch) check
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the signal irq_trigger for pending interrupts and branch to state
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the signal irq_trigger for pending interrupts and branch to state
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15 (interrupt) if it is set. This should NOT be done if the current
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15 (interrupt) if it is set. This should NOT be done if the current
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state could possibly set the PSW to disable interrupts. So states
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state could possibly set the PSW to disable interrupts. So states
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15 (interrupt), 22 (mvts), 23 (rfx), and 24 (trap) don't do this
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15 (interrupt), 22 (mvts), 23 (rfx), and 24 (trap) don't do this
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check any longer. On the other hand, delaying the acceptance of
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check any longer. On the other hand, delaying the acceptance of
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a pending interrupt for a whole instruction would come as a hard
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a pending interrupt for a whole instruction would come as a hard
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surprise for an unsuspecting system programmer. It would in fact
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surprise for an unsuspecting system programmer. It would in fact
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be possible to write an instruction sequence which never accepts
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be possible to write an instruction sequence which never accepts
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any interrupts, although interrupts are expected to be enabled for
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any interrupts, although interrupts are expected to be enabled for
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one instruction:
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one instruction:
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mvts $5,PSW ; disable interrupts
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mvts $5,PSW ; disable interrupts
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label:
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label:
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mvts $4,PSW ; enable interrupts
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mvts $4,PSW ; enable interrupts
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mvts $5,PSW ; disable interrupts
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mvts $5,PSW ; disable interrupts
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j label
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j label
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This cannot be tolerated. Therefore an additional state is inserted,
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This cannot be tolerated. Therefore an additional state is inserted,
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just to check irq_trigger, computed from the new value of the PSW.
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just to check irq_trigger, computed from the new value of the PSW.
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This certainly makes no sense for interrupt and trap, because the new
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This certainly makes no sense for interrupt and trap, because the new
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value of the interrupt enable flag in the PSW is known to be 0. So
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value of the interrupt enable flag in the PSW is known to be 0. So
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the new state is only reached from states 22 (mvts) and 23 (rfx).
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the new state is only reached from states 22 (mvts) and 23 (rfx).
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First, I did some renumbering of states:
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First, I did some renumbering of states:
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Renamed state 25 to 26 (TLB instruction).
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Renamed state 25 to 26 (TLB instruction).
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Renamed state 24 to 25 (trap).
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Renamed state 24 to 25 (trap).
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Then the additional state is called state 24.
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Then the additional state is called state 24.
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c) Because the trap instruction is merely one of several possible causes
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c) Because the trap instruction is merely one of several possible causes
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for an exception, its execution state (25, see step b) above) can be
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for an exception, its execution state (25, see step b) above) can be
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used to implement exceptions. The exception number must be communicated
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used to implement exceptions. The exception number must be communicated
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to this state. We therefore have a 4-bit register named 'exc_priority'
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to this state. We therefore have a 4-bit register named 'exc_priority'
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which must be set by any state transition to state 25. Its contents
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which must be set by any state transition to state 25. Its contents
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are appended to a leading 1 and then represent the exception priority
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are appended to a leading 1 and then represent the exception priority
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which is found in the PSW.
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which is found in the PSW.
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d) The following exceptions are implemented:
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d) The following exceptions are implemented:
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trap instruction exception
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trap instruction exception
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illegal instruction exception
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illegal instruction exception
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divide instruction exception
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divide instruction exception
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e) The 'bus timeout exception' is implemented with the help of a counter
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e) The 'bus timeout exception' is implemented with the help of a counter
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which is activated if the bus is enabled and its wait line active.
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which is activated if the bus is enabled and its wait line active.
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When the counter expires, the exception execution state is entered.
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When the counter expires, the exception execution state is entered.
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There is a catch: if the bus timeout occurs during instruction fetch,
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There is a catch: if the bus timeout occurs during instruction fetch,
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the PC has yet its old value, i.e., it must not get decremented while
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the PC has yet its old value, i.e., it must not get decremented while
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handling the exception. This could be handled best by just another
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handling the exception. This could be handled best by just another
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state (renaming state 26 to 27, and using the new state 26 for
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state (renaming state 26 to 27, and using the new state 26 for
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exception handling without decrementing the PC).
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exception handling without decrementing the PC).
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f) The 'privileged instruction exception' isn't difficult to implement
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f) The 'privileged instruction exception' isn't difficult to implement
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but can only be tested if a TLB is present (because the test program
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but can only be tested if a TLB is present (because the test program
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must enter user mode in order to trigger the exception - and in user
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must enter user mode in order to trigger the exception - and in user
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mode, instructions cannot be executed at addresses which have their
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mode, instructions cannot be executed at addresses which have their
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MSB set without triggering a 'privileged address exception').
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MSB set without triggering a 'privileged address exception').
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eco32-18
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eco32-18
|
--------
|
--------
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|
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This intermediate version got a new bus controller which does no longer
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This intermediate version got a new bus controller which does no longer
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mirror RAM and ROM in their respective upper address spaces but signals
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mirror RAM and ROM in their respective upper address spaces but signals
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a bus timeout instead.
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a bus timeout instead.
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eco32-19
|
eco32-19
|
--------
|
--------
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|
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This version implements the MMU with a TLB (first of two parts).
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This version implements the MMU with a TLB (first of two parts).
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a) Add the TLB module. It consists of an "input section" (32 comparators
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a) Add the TLB module. It consists of an "input section" (32 comparators
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working in parallel, and a priority encoder which computes the binary
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working in parallel, and a priority encoder which computes the binary
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representation of the number of one of the matching comparators), and
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representation of the number of one of the matching comparators), and
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an "output section" which merely delivers the previously stored frame
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an "output section" which merely delivers the previously stored frame
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number and permission bits of the frame. The output section's memory
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number and permission bits of the frame. The output section's memory
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is addressed by the output of the priority encoder. The two sections
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is addressed by the output of the priority encoder. The two sections
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together implement a fully associative address translation cache.
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together implement a fully associative address translation cache.
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b) Change the MMU from a purely combinational circuit to one which needs
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b) Change the MMU from a purely combinational circuit to one which needs
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a single clock cycle to compute its output. This is necessary because
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a single clock cycle to compute its output. This is necessary because
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the RAM which stores frame numbers in the TLB output section also needs
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the RAM which stores frame numbers in the TLB output section also needs
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one cycle to read its contents.
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one cycle to read its contents.
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c) In the controller of the CPU add one state before each bus cycle state
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c) In the controller of the CPU add one state before each bus cycle state
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(i.e., three states: fetch, load, and store). These additional states
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(i.e., three states: fetch, load, and store). These additional states
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perform the address translation from a virtual to a physical address.
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perform the address translation from a virtual to a physical address.
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I added three new states (28..30) which now implement the bus cycles
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I added three new states (28..30) which now implement the bus cycles
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and reassigned the old state numbers (1, 12, 14) to the states which
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and reassigned the old state numbers (1, 12, 14) to the states which
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do address translations.
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do address translations.
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d) The MMU must implement several functions:
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d) The MMU must implement several functions:
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no operation, hold output
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no operation, hold output
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map virtual to physical address
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map virtual to physical address
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execute tbs
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execute tbs
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execute tbwr
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execute tbwr
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execute tbri
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execute tbri
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execute tbwi
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execute tbwi
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The controller instructs the MMU which function is to be executed.
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The controller instructs the MMU which function is to be executed.
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|
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e) The tbwr instruction needs a "random" index. This can be generated
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e) The tbwr instruction needs a "random" index. This can be generated
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by a counter which counts down at every clock pulse, instruction
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by a counter which counts down at every clock pulse, instruction
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fetch, or address mapping request. There is a catch: if the counter
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fetch, or address mapping request. There is a catch: if the counter
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would count on every clock pulse and each instruction would need a
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would count on every clock pulse and each instruction would need a
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multiple of 2 clock pulses to complete, then only half the entries
|
multiple of 2 clock pulses to complete, then only half the entries
|
of the TLB would be used. Thus counting instructions is safer, and
|
of the TLB would be used. Thus counting instructions is safer, and
|
furthermore counting address mappings is cheaper than that (because
|
furthermore counting address mappings is cheaper than that (because
|
address mapping is already one of the functions of the MMU and
|
address mapping is already one of the functions of the MMU and
|
therefore easily detectable).
|
therefore easily detectable).
|
|
|
f) The values of the special registers 1 (TLB Index), 2 (TLB EntryHi),
|
f) The values of the special registers 1 (TLB Index), 2 (TLB EntryHi),
|
and 3 (TLB EntryLo) are needed within the MMU. The MMU also must
|
and 3 (TLB EntryLo) are needed within the MMU. The MMU also must
|
write new values to these registers under certain circumstances.
|
write new values to these registers under certain circumstances.
|
Three dedicated signals for each of these special registers (old
|
Three dedicated signals for each of these special registers (old
|
value, write enable, new value) enable the MMU to do so.
|
value, write enable, new value) enable the MMU to do so.
|
|
|
g) In principle, the tbri instruction needs two clock cycles to do
|
g) In principle, the tbri instruction needs two clock cycles to do
|
its work: one cycle to read the TLB and another one to write the
|
its work: one cycle to read the TLB and another one to write the
|
data to special register 3. This can be reduced to a single clock
|
data to special register 3. This can be reduced to a single clock
|
cycle (write to special register 3) if the RAM's contents are read
|
cycle (write to special register 3) if the RAM's contents are read
|
out by default within every clock cycle.
|
out by default within every clock cycle.
|
|
|
|
|
eco32-20
|
eco32-20
|
--------
|
--------
|
|
|
This version implements the MMU with a TLB (second of two parts).
|
This version implements the MMU with a TLB (second of two parts).
|
|
|
a) Detect privileged and illegal address exceptions within the state
|
a) Detect privileged and illegal address exceptions within the state
|
machine. In order to do so, virtual address bits 31, 1, and 0 must
|
machine. In order to do so, virtual address bits 31, 1, and 0 must
|
be available there. The exceptions are detected in the address
|
be available there. The exceptions are detected in the address
|
translation states (1, 12, 14). Control is transferred to state
|
translation states (1, 12, 14). Control is transferred to state
|
25 (or 26 in case of violation during instruction fetch) with
|
25 (or 26 in case of violation during instruction fetch) with
|
exc_priority set accordingly. Although not yet needed for the bus,
|
exc_priority set accordingly. Although not yet needed for the bus,
|
the bus size lines must be set to the intended transfer width
|
the bus size lines must be set to the intended transfer width
|
already in the translation states in order to detect illegal
|
already in the translation states in order to detect illegal
|
addresses there (before the bus is actually accessed). Last but
|
addresses there (before the bus is actually accessed). Last but
|
not least the MMU must not try to map an address if that triggered
|
not least the MMU must not try to map an address if that triggered
|
one of the two exceptions.
|
one of the two exceptions.
|
|
|
b) The TLB supplies three control signals (tlb_missed, tlb_invalid,
|
b) The TLB supplies three control signals (tlb_missed, tlb_invalid,
|
and tlb_wrtprot) which are needed to detect the three exceptions
|
and tlb_wrtprot) which are needed to detect the three exceptions
|
"TLB miss", "TLB entry invalid", and "page frame write protected".
|
"TLB miss", "TLB entry invalid", and "page frame write protected".
|
The first of these, tlb_missed, is generated in the "input section"
|
The first of these, tlb_missed, is generated in the "input section"
|
of the TLB and has to be delayed for one clock cycle so that it
|
of the TLB and has to be delayed for one clock cycle so that it
|
appears at the TLB output at the same time the other two signals do.
|
appears at the TLB output at the same time the other two signals do.
|
The three signals are routed to the CPU's state machine. Because
|
The three signals are routed to the CPU's state machine. Because
|
they are valid only after the address translation took place (the
|
they are valid only after the address translation took place (the
|
valid and write bits are stored together with the frame number),
|
valid and write bits are stored together with the frame number),
|
the error conditions can only be detected in the bus cycle states.
|
the error conditions can only be detected in the bus cycle states.
|
The actual bus cycle however must suppress its bus enable signal,
|
The actual bus cycle however must suppress its bus enable signal,
|
if any exception has been detected.
|
if any exception has been detected.
|
Attention: the three control signals must be de-asserted if the
|
Attention: the three control signals must be de-asserted if the
|
address in question is directly mapped (i.e., has its two MSBs set).
|
address in question is directly mapped (i.e., has its two MSBs set).
|
|
|
c) The tlb_missed signal has in fact to be splitted into two signals:
|
c) The tlb_missed signal has in fact to be splitted into two signals:
|
tlb_kmissed (MSB of address is 1) and tlb_umissed (MSB is 0). This
|
tlb_kmissed (MSB of address is 1) and tlb_umissed (MSB is 0). This
|
must be done in order to route "user TLB misses" to another start
|
must be done in order to route "user TLB misses" to another start
|
address. Furthermore, the V bit in the PSW has to be considered and
|
address. Furthermore, the V bit in the PSW has to be considered and
|
the ISR start address modified accordingly.
|
the ISR start address modified accordingly.
|
|
|
d) The three write enable signals for the three special TLB registers
|
d) The three write enable signals for the three special TLB registers
|
are best produced within the main CPU state machine, because they
|
are best produced within the main CPU state machine, because they
|
are dependent on the opcode if one of the TLB instructions is
|
are dependent on the opcode if one of the TLB instructions is
|
executed. They must also be asserted according to any exception
|
executed. They must also be asserted according to any exception
|
which das been detected.
|
which das been detected.
|
|
|
|
|
eco32-21
|
eco32-21
|
--------
|
--------
|
|
|
I changed the display description from a schematic to plain Verilog.
|
I changed the display description from a schematic to plain Verilog.
|
|
|
|
|
eco32-22
|
eco32-22
|
--------
|
--------
|
|
|
The display has got character attributes: one attribute byte per
|
The display has got character attributes: one attribute byte per
|
character stored in the display memory. The bits in the attribute
|
character stored in the display memory. The bits in the attribute
|
byte are loosely imitating those from the good old CGA adapter in
|
byte are loosely imitating those from the good old CGA adapter in
|
text mode.
|
text mode.
|
Bit 7: blinking foreground
|
Bit 7: blinking foreground
|
Bit 6: background red
|
Bit 6: background red
|
Bit 5: background green
|
Bit 5: background green
|
Bit 4: background blue
|
Bit 4: background blue
|
Bit 3: intensified foreground
|
Bit 3: intensified foreground
|
Bit 2: foreground red
|
Bit 2: foreground red
|
Bit 1: foreground green
|
Bit 1: foreground green
|
Bit 0: foreground blue
|
Bit 0: foreground blue
|
|
|
|
|
eco32-23
|
eco32-23
|
--------
|
--------
|
|
|
Now the keyboard can interrupt the CPU.
|
Now the keyboard can interrupt the CPU.
|
|
|
|
|
eco32-24
|
eco32-24
|
--------
|
--------
|
|
|
Project re-organized. All source files are now located under a single
|
Project re-organized. All source files are now located under a single
|
directory "src". Now it is easier to clean up a project after editing
|
directory "src". Now it is easier to clean up a project after editing
|
or testing: simply remove all files and directories except "src" and
|
or testing: simply remove all files and directories except "src" and
|
the project manager's control file "eco32.npl".
|
the project manager's control file "eco32.npl".
|
|
|
|
|
eco32-25
|
eco32-25
|
--------
|
--------
|
|
|
The reset circuit had the following problem: although an externally
|
The reset circuit had the following problem: although an externally
|
applied reset signal (produced by pressing the "reset" pushbutton)
|
applied reset signal (produced by pressing the "reset" pushbutton)
|
was internally recognized for initializing the CPU, it did not work
|
was internally recognized for initializing the CPU, it did not work
|
the other way around, which is important when re-loading the FPGA.
|
the other way around, which is important when re-loading the FPGA.
|
In this case, the CPU was reset, but the external devices, especially
|
In this case, the CPU was reset, but the external devices, especially
|
the disk drive, did not get a reset signal. So the drive could get
|
the disk drive, did not get a reset signal. So the drive could get
|
out of sync with its controller. The reset circuit now actively drives
|
out of sync with its controller. The reset circuit now actively drives
|
the external bidirectional reset line when performing a reset, as well
|
the external bidirectional reset line when performing a reset, as well
|
as observing this line when not actively driving it.
|
as observing this line when not actively driving it.
|
|
|
|
|
eco32-26
|
eco32-26
|
--------
|
--------
|
|
|
This is the first version with a real IDE disk attached! Thanks to
|
This is the first version with a real IDE disk attached! Thanks to
|
Martin Geisse, who did a very nice job.
|
Martin Geisse, who did a very nice job.
|
|
|
|
|
eco32-27
|
eco32-27
|
--------
|
--------
|
|
|
The two serial interfaces are now able to generate interrupt requests.
|
The two serial interfaces are now able to generate interrupt requests.
|
As far as I can see, the implementation is now functionally complete.
|
As far as I can see, the implementation is now functionally complete.
|
|
|
|
|
eco32-28
|
eco32-28
|
--------
|
--------
|
|
|
The IDE disk interface had a small problem with reading/writing a block
|
The IDE disk interface had a small problem with reading/writing a block
|
of 8 sectors in a single operation. Fixed.
|
of 8 sectors in a single operation. Fixed.
|
|
|
|
|
eco32-29
|
eco32-29
|
--------
|
--------
|
|
|
Same as eco32-28, but with an ISE Version 11 project file. Because
|
Same as eco32-28, but with an ISE Version 11 project file. Because
|
it is now possible to develop exclusively under Linux (including
|
it is now possible to develop exclusively under Linux (including
|
download to the FPGA board), all source files were converted to
|
download to the FPGA board), all source files were converted to
|
newline-only line endings.
|
newline-only line endings.
|
|
|
|
|
