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Rev 299 |
//
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//
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// dac.v -- DAC control circuit
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// dac.v -- DAC control circuit
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//
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//
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`timescale 1ns/1ns
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`timescale 1ns/10ps
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`default_nettype none
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`default_nettype none
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module dac(clk, reset,
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module dac(clk, reset,
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sample_l, sample_r, next,
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sample_l, sample_r, next,
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sck, sdi, ld);
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sck, sdi, ld);
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input clk;
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input clk;
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input reset;
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input reset;
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input [15:0] sample_l;
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input [15:0] sample_l;
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input [15:0] sample_r;
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input [15:0] sample_r;
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output next;
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output next;
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output sck;
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output sck;
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output sdi;
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output sdi;
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output reg ld;
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output reg ld;
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reg [9:0] timing;
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reg [9:0] timing;
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reg [47:0] sr;
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reg [47:0] sr;
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wire shift;
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wire shift;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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timing <= 10'h0;
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timing <= 10'h0;
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end else begin
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end else begin
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timing <= timing + 1;
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timing <= timing + 1;
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end
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end
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end
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end
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assign sck = timing[0];
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assign sck = timing[0];
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assign next = (timing[9:0] == 10'h001) ? 1 : 0;
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assign next = (timing[9:0] == 10'h001) ? 1 : 0;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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ld <= 1'b1;
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ld <= 1'b1;
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end else begin
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end else begin
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if (timing[9:0] == 10'h001) begin
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if (timing[9:0] == 10'h001) begin
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ld <= 1'b0;
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ld <= 1'b0;
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end
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end
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if (timing[9:0] == 10'h031) begin
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if (timing[9:0] == 10'h031) begin
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ld <= 1'b1;
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ld <= 1'b1;
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end
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end
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if (timing[9:0] == 10'h033) begin
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if (timing[9:0] == 10'h033) begin
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ld <= 1'b0;
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ld <= 1'b0;
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end
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end
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if (timing[9:0] == 10'h063) begin
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if (timing[9:0] == 10'h063) begin
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ld <= 1'b1;
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ld <= 1'b1;
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end
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end
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end
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end
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end
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end
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assign shift = sck & ~ld;
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assign shift = sck & ~ld;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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sr <= 48'h0;
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sr <= 48'h0;
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end else begin
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end else begin
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if (next) begin
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if (next) begin
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sr[47:44] <= 4'b0011;
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sr[47:44] <= 4'b0011;
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sr[43:40] <= 4'b0000;
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sr[43:40] <= 4'b0000;
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sr[39:24] <= { ~sample_l[15],
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sr[39:24] <= { ~sample_l[15],
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sample_l[14:0] };
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sample_l[14:0] };
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sr[23:20] <= 4'b0011;
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sr[23:20] <= 4'b0011;
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sr[19:16] <= 4'b0001;
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sr[19:16] <= 4'b0001;
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sr[15: 0] <= { ~sample_r[15],
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sr[15: 0] <= { ~sample_r[15],
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sample_r[14:0] };
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sample_r[14:0] };
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end else begin
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end else begin
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if (shift) begin
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if (shift) begin
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sr[47:1] <= sr[46:0];
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sr[47:1] <= sr[46:0];
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sr[0] <= 1'b0;
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sr[0] <= 1'b0;
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end
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end
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end
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end
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end
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end
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end
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end
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assign sdi = sr[47];
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assign sdi = sr[47];
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endmodule
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endmodule
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