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Rev 299 |
//
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//
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// dac_test.v -- test bench for DAC control circuit
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// dac_test.v -- test bench for DAC control circuit
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//
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//
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`include "dac.v"
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`timescale 1ns/10ps
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`timescale 1ns/1ns
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`default_nettype none
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`default_nettype none
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module dac_test;
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module dac_test;
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reg clk; // system clock (50 MHz)
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reg clk; // system clock (50 MHz)
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reg reset_in; // reset, input
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reg reset_in; // reset, input
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reg reset_s1; // reset, first synchronizer
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reg reset_s1; // reset, first synchronizer
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reg reset; // reset, second synchronizer
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reg reset; // reset, second synchronizer
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reg [15:0] sample_l;
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reg [15:0] sample_l;
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reg [15:0] sample_r;
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reg [15:0] sample_r;
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wire next;
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wire next;
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wire sck;
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wire sck;
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wire sdi;
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wire sdi;
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wire ld;
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wire ld;
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// instantiate the controller
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// instantiate the controller
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dac dac_1(clk, reset,
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dac dac_1(clk, reset,
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sample_l, sample_r, next,
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sample_l, sample_r, next,
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sck, sdi, ld);
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sck, sdi, ld);
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// simulation control
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// simulation control
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initial begin
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initial begin
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#0 $dumpfile("dump.vcd");
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#0 $dumpfile("dump.vcd");
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$dumpvars(0, dac_test);
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$dumpvars(0, dac_test);
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sample_l = 16'h0FF0;
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sample_l = 16'h0FF0;
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sample_r = 16'hAA55;
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sample_r = 16'hAA55;
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clk = 1;
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clk = 1;
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reset_in = 1;
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reset_in = 1;
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#145 reset_in = 0;
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#145 reset_in = 0;
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#90000 $finish;
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#90000 $finish;
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end
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end
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// clock generator
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// clock generator
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always begin
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always begin
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#10 clk = ~clk; // 20 nsec cycle time
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#10 clk = ~clk; // 20 nsec cycle time
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end
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end
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// reset synchronizer
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// reset synchronizer
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always @(posedge clk) begin
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always @(posedge clk) begin
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reset_s1 <= reset_in;
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reset_s1 <= reset_in;
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reset <= reset_s1;
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reset <= reset_s1;
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end
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end
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endmodule
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endmodule
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