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Rev 290 |
//
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//
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// dac.v -- DAC control circuit
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// dac.v -- DAC control circuit
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//
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//
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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`default_nettype none
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module dac(clk, reset,
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module dac(clk, reset,
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sample_l, sample_r, next,
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sample_l, sample_r, next,
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mclk, sclk, lrck, sdti);
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mclk, sclk, lrck, sdti);
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input clk;
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input clk;
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input reset;
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input reset;
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input [15:0] sample_l;
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input [15:0] sample_l;
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input [15:0] sample_r;
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input [15:0] sample_r;
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output next;
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output next;
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output mclk;
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output mclk;
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output sclk;
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output sclk;
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output lrck;
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output lrck;
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output sdti;
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output sdti;
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reg [9:0] timing;
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reg [9:0] timing;
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reg [63:0] sr;
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reg [63:0] sr;
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wire shift;
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wire shift;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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timing <= 10'h0;
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timing <= 10'h0;
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end else begin
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end else begin
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timing <= timing + 1;
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timing <= timing + 1;
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end
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end
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end
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end
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assign mclk = timing[1];
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assign mclk = timing[1];
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assign sclk = timing[3];
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assign sclk = timing[3];
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assign lrck = timing[9];
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assign lrck = timing[9];
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assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;
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assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;
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assign shift = (timing[3:0] == 4'hF) ? 1 : 0;
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assign shift = (timing[3:0] == 4'hF) ? 1 : 0;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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sr <= 64'h0;
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sr <= 64'h0;
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end else begin
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end else begin
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if (next) begin
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if (next) begin
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sr[63:52] <= 12'h000;
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sr[63:52] <= 12'h000;
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sr[51:32] <= { sample_l[15:0], 4'h0 };
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sr[51:32] <= { sample_l[15:0], 4'h0 };
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sr[31:20] <= 12'h000;
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sr[31:20] <= 12'h000;
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sr[19: 0] <= { sample_r[15:0], 4'h0 };
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sr[19: 0] <= { sample_r[15:0], 4'h0 };
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end else begin
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end else begin
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if (shift) begin
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if (shift) begin
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sr[63:1] <= sr[62:0];
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sr[63:1] <= sr[62:0];
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sr[0] <= 1'b0;
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sr[0] <= 1'b0;
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end
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end
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end
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end
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end
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end
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end
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end
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assign sdti = sr[63];
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assign sdti = sr[63];
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endmodule
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endmodule
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