//
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//
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// atabuf.v -- parallel ATA data buffer
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// atabuf.v -- parallel ATA data buffer
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//
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//
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`timescale 1ns/10ps
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`default_nettype none
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module ata_buffer (clk,
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module ata_buffer (clk,
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bus_write, bus_addr, bus_din, bus_dout,
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bus_write, bus_addr, bus_din, bus_dout,
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ata_write, ata_addr, ata_din, ata_dout);
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ata_write, ata_addr, ata_din, ata_dout);
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input clk;
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input clk;
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// bus interface
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// bus interface
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input bus_write;
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input bus_write;
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input [11:2] bus_addr;
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input [11:2] bus_addr;
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input [31:0] bus_din;
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input [31:0] bus_din;
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output [31:0] bus_dout;
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output [31:0] bus_dout;
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// ata interface
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// ata interface
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input ata_write;
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input ata_write;
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input [11:1] ata_addr;
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input [11:1] ata_addr;
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input [15:0] ata_din;
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input [15:0] ata_din;
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output [15:0] ata_dout;
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output [15:0] ata_dout;
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wire [9:0] internal_bus_addr;
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wire [9:0] internal_bus_addr;
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wire [9:0] internal_ata_addr;
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wire [9:0] internal_ata_addr;
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wire [15:0] lo_din_bus;
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wire [15:0] lo_din_bus;
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wire [15:0] hi_din_bus;
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wire [15:0] hi_din_bus;
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wire [15:0] lo_din_ata;
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wire [15:0] lo_din_ata;
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wire [15:0] hi_din_ata;
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wire [15:0] hi_din_ata;
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wire [15:0] lo_dout_bus;
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wire [15:0] lo_dout_bus;
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wire [15:0] hi_dout_bus;
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wire [15:0] hi_dout_bus;
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wire [15:0] lo_dout_ata;
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wire [15:0] lo_dout_ata;
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wire [15:0] hi_dout_ata;
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wire [15:0] hi_dout_ata;
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wire lo_write_bus;
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wire lo_write_bus;
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wire hi_write_bus;
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wire hi_write_bus;
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wire lo_write_ata;
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wire lo_write_ata;
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wire hi_write_ata;
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wire hi_write_ata;
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reg ata_out_muxctrl;
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reg ata_out_muxctrl;
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assign internal_bus_addr[9:0] = bus_addr[11:2];
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assign internal_bus_addr[9:0] = bus_addr[11:2];
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assign internal_ata_addr[9:0] = ata_addr[11:2];
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assign internal_ata_addr[9:0] = ata_addr[11:2];
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assign lo_din_bus = { bus_din[7:0], bus_din[15:8] };
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assign lo_din_bus = { bus_din[7:0], bus_din[15:8] };
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assign hi_din_bus = { bus_din[23:16], bus_din[31:24] };
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assign hi_din_bus = { bus_din[23:16], bus_din[31:24] };
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assign lo_din_ata = ata_din;
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assign lo_din_ata = ata_din;
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assign hi_din_ata = ata_din;
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assign hi_din_ata = ata_din;
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// pipeline register for ata output mux control
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// pipeline register for ata output mux control
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always @(posedge clk) begin
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always @(posedge clk) begin
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ata_out_muxctrl <= ata_addr[1];
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ata_out_muxctrl <= ata_addr[1];
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end
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end
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assign bus_dout = { hi_dout_bus[7:0], hi_dout_bus[15:8],
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assign bus_dout = { hi_dout_bus[7:0], hi_dout_bus[15:8],
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lo_dout_bus[7:0], lo_dout_bus[15:8] };
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lo_dout_bus[7:0], lo_dout_bus[15:8] };
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assign ata_dout = ata_out_muxctrl ? lo_dout_ata : hi_dout_ata;
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assign ata_dout = ata_out_muxctrl ? lo_dout_ata : hi_dout_ata;
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assign lo_write_bus = bus_write;
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assign lo_write_bus = bus_write;
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assign hi_write_bus = bus_write;
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assign hi_write_bus = bus_write;
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assign lo_write_ata = ata_write & ata_addr[1];
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assign lo_write_ata = ata_write & ata_addr[1];
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assign hi_write_ata = ata_write & ~ata_addr[1];
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assign hi_write_ata = ata_write & ~ata_addr[1];
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RAMB16_S18_S18 lo_buffer (
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RAMB16_S18_S18 lo_buffer (
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.DOA(lo_dout_bus),
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.DOA(lo_dout_bus),
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.DOB(lo_dout_ata),
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.DOB(lo_dout_ata),
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.ADDRA(internal_bus_addr),
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.ADDRA(internal_bus_addr),
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.ADDRB(internal_ata_addr),
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.ADDRB(internal_ata_addr),
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.CLKA(clk),
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.CLKA(clk),
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.CLKB(clk),
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.CLKB(clk),
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.DIA(lo_din_bus),
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.DIA(lo_din_bus),
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.DIB(lo_din_ata),
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.DIB(lo_din_ata),
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.DIPA(2'b00),
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.DIPA(2'b00),
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.DIPB(2'b00),
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.DIPB(2'b00),
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.ENA(1'b1),
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.ENA(1'b1),
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.ENB(1'b1),
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.ENB(1'b1),
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.SSRA(1'b0),
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.SSRA(1'b0),
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.SSRB(1'b0),
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.SSRB(1'b0),
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.WEA(lo_write_bus),
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.WEA(lo_write_bus),
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.WEB(lo_write_ata)
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.WEB(lo_write_ata)
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);
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);
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RAMB16_S18_S18 hi_buffer (
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RAMB16_S18_S18 hi_buffer (
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.DOA(hi_dout_bus),
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.DOA(hi_dout_bus),
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.DOB(hi_dout_ata),
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.DOB(hi_dout_ata),
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.ADDRA(internal_bus_addr),
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.ADDRA(internal_bus_addr),
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.ADDRB(internal_ata_addr),
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.ADDRB(internal_ata_addr),
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.CLKA(clk),
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.CLKA(clk),
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.CLKB(clk),
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.CLKB(clk),
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.DIA(hi_din_bus),
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.DIA(hi_din_bus),
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.DIB(hi_din_ata),
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.DIB(hi_din_ata),
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.DIPA(2'b00),
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.DIPA(2'b00),
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.DIPB(2'b00),
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.DIPB(2'b00),
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.ENA(1'b1),
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.ENA(1'b1),
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.ENB(1'b1),
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.ENB(1'b1),
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.SSRA(1'b0),
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.SSRA(1'b0),
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.SSRB(1'b0),
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.SSRB(1'b0),
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.WEA(hi_write_bus),
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.WEA(hi_write_bus),
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.WEB(hi_write_ata)
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.WEB(hi_write_ata)
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);
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);
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endmodule
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endmodule
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