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https://opencores.org/ocsvn/eco32/eco32/trunk
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| Rev 14 |
Rev 148 |
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; sregtest.s -- test special register transfer instructions
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; sregtest.s -- test special register transfer instructions
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;
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;
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.set io_base,0xF0300000
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.set io_base,0xF0300000
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add $7,$0,'.'
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add $7,$0,'.'
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add $11,$0,0x1E67C536
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add $11,$0,0x1E67C536
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mvts $11,1
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mvts $11,1
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add $12,$0,0xB45FCC78
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add $12,$0,0xB45FCC78
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mvts $12,2
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mvts $12,2
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add $13,$0,0x1FCB0BC5
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add $13,$0,0x1FCB0BC5
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mvts $13,3
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mvts $13,3
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add $14,$0,0x3AE82DD4
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mvts $14,4
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mvfs $8,1
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mvfs $8,1
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xor $9,$8,$11
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xor $9,$8,$11
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and $9,$9,0x0000001F
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and $9,$9,0x0000001F
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beq $9,$0,lbl1
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beq $9,$0,lbl1
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add $7,$0,'?'
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add $7,$0,'?'
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lbl1:
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lbl1:
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mvfs $8,2
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mvfs $8,2
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xor $9,$8,$12
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xor $9,$8,$12
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and $9,$9,0xFFFFF000
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and $9,$9,0xFFFFF000
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beq $9,$0,lbl2
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beq $9,$0,lbl2
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add $7,$0,'?'
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add $7,$0,'?'
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lbl2:
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lbl2:
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mvfs $8,3
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mvfs $8,3
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xor $9,$8,$13
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xor $9,$8,$13
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and $9,$9,0x3FFFF003
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and $9,$9,0x3FFFF003
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beq $9,$0,lbl3
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beq $9,$0,lbl3
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add $7,$0,'?'
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add $7,$0,'?'
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lbl3:
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lbl3:
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mvfs $8,4
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xor $9,$8,$14
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and $9,$9,0xFFFFFFFF
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beq $9,$0,lbl4
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add $7,$0,'?'
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lbl4:
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jal out
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jal out
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halt:
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halt:
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j halt
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j halt
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out:
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out:
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add $8,$0,io_base
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add $8,$0,io_base
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out1:
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out1:
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ldw $9,$8,8
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ldw $9,$8,8
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and $9,$9,1
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and $9,$9,1
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beq $9,$0,out1
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beq $9,$0,out1
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stw $7,$8,12
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stw $7,$8,12
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jr $31
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jr $31
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