;
|
;
|
; start.s -- ECO32 ROM monitor startup and support routines
|
; start.s -- ECO32 ROM monitor startup and support routines
|
;
|
;
|
|
|
.set BIO_BASE,0xF1000000 ; board I/O base address
|
.set BIO_BASE,0xF1000000 ; board I/O base address
|
.set BIO_WR,BIO_BASE+0
|
.set BIO_WR,BIO_BASE+0
|
.set BIO_RD,BIO_BASE+4
|
.set BIO_RD,BIO_BASE+4
|
.set CIO_CTRL,0x08 ; this bit controls console I/O
|
.set CIO_CTRL,0x08 ; this bit controls console I/O
|
|
|
.set CIO_KBD_DSP,0x00 ; set console to keyboard/display
|
.set CIO_KBD_DSP,0x00 ; set console to keyboard/display
|
.set CIO_SERIAL_0,0x03 ; set console to serial line 0
|
.set CIO_SERIAL_0,0x03 ; set console to serial line 0
|
|
|
.set dmapaddr,0xC0000000 ; base of directly mapped addresses
|
.set dmapaddr,0xC0000000 ; base of directly mapped addresses
|
.set stacktop,0xC0010000 ; monitor stack is at top of 64K
|
.set stacktop,0xC0010000 ; monitor stack is at top of 64K
|
|
|
.set PSW,0 ; reg # of PSW
|
.set PSW,0 ; reg # of PSW
|
.set V_SHIFT,27 ; interrupt vector ctrl bit
|
.set V_SHIFT,27 ; interrupt vector ctrl bit
|
.set V,1 << V_SHIFT
|
.set V,1 << V_SHIFT
|
|
|
.set TLB_INDEX,1 ; reg # of TLB Index
|
.set TLB_INDEX,1 ; reg # of TLB Index
|
.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
|
.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
|
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
|
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
|
.set TLB_ENTRIES,32 ; number of TLB entries
|
.set TLB_ENTRIES,32 ; number of TLB entries
|
.set BAD_ADDRESS,4 ; reg # of bad address reg
|
.set BAD_ADDRESS,4 ; reg # of bad address reg
|
.set BAD_ACCESS,5 ; reg # of bad access reg
|
.set BAD_ACCESS,5 ; reg # of bad access reg
|
|
|
.set USER_CONTEXT_SIZE,38*4 ; size of user context
|
.set USER_CONTEXT_SIZE,38*4 ; size of user context
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.import _ecode
|
.import _ecode
|
.import _edata
|
.import _edata
|
.import _ebss
|
.import _ebss
|
|
|
.import kbdinit
|
.import kbdinit
|
.import kbdinchk
|
.import kbdinchk
|
.import kbdin
|
.import kbdin
|
|
|
.import dspinit
|
.import dspinit
|
.import dspoutchk
|
.import dspoutchk
|
.import dspout
|
.import dspout
|
|
|
.import ser0init
|
.import ser0init
|
.import ser0inchk
|
.import ser0inchk
|
.import ser0in
|
.import ser0in
|
.import ser0outchk
|
.import ser0outchk
|
.import ser0out
|
.import ser0out
|
|
|
.import ser1init
|
.import ser1init
|
.import ser1inchk
|
.import ser1inchk
|
.import ser1in
|
.import ser1in
|
.import ser1outchk
|
.import ser1outchk
|
.import ser1out
|
.import ser1out
|
|
|
.import dskinitctl
|
.import dskinitctl
|
.import dskcapctl
|
.import dskcapctl
|
.import dskioctl
|
.import dskioctl
|
|
|
.import dskinitser
|
.import dskinitser
|
.import dskcapser
|
.import dskcapser
|
.import dskioser
|
.import dskioser
|
|
|
.import main
|
.import main
|
|
|
.export _bcode
|
.export _bcode
|
.export _bdata
|
.export _bdata
|
.export _bbss
|
.export _bbss
|
|
|
.export setcon
|
.export setcon
|
.export cinchk
|
.export cinchk
|
.export cin
|
.export cin
|
.export coutchk
|
.export coutchk
|
.export cout
|
.export cout
|
.export dskcap
|
.export dskcap
|
.export dskio
|
.export dskio
|
|
|
.export getTLB_HI
|
.export getTLB_HI
|
.export getTLB_LO
|
.export getTLB_LO
|
.export setTLB
|
.export setTLB
|
|
|
.export saveState
|
.export saveState
|
.export monitorReturn
|
.export monitorReturn
|
|
|
.import userContext
|
.import userContext
|
.export resume
|
.export resume
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
_bcode:
|
_bcode:
|
|
|
.data
|
.data
|
_bdata:
|
_bdata:
|
|
|
.bss
|
.bss
|
_bbss:
|
_bbss:
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
startup:
|
startup:
|
j start
|
j start
|
|
|
interrupt:
|
interrupt:
|
j debug
|
j debug
|
|
|
userMiss:
|
userMiss:
|
j debug
|
j debug
|
|
|
monitor:
|
monitor:
|
j debug
|
j debug
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
setcon:
|
setcon:
|
j setcio
|
j setcio
|
|
|
cinchk:
|
cinchk:
|
j cichk
|
j cichk
|
|
|
cin:
|
cin:
|
j ci
|
j ci
|
|
|
coutchk:
|
coutchk:
|
j cochk
|
j cochk
|
|
|
cout:
|
cout:
|
j co
|
j co
|
|
|
dskcap:
|
dskcap:
|
j dcap
|
j dcap
|
|
|
dskio:
|
dskio:
|
j dio
|
j dio
|
|
|
reserved_11:
|
reserved_11:
|
j reserved_11
|
j reserved_11
|
|
|
reserved_12:
|
reserved_12:
|
j reserved_12
|
j reserved_12
|
|
|
reserved_13:
|
reserved_13:
|
j reserved_13
|
j reserved_13
|
|
|
reserved_14:
|
reserved_14:
|
j reserved_14
|
j reserved_14
|
|
|
reserved_15:
|
reserved_15:
|
j reserved_15
|
j reserved_15
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
start:
|
start:
|
; let irq/exc vectors point to RAM
|
; let irq/exc vectors point to RAM
|
add $8,$0,V
|
add $8,$0,V
|
mvts $8,PSW
|
mvts $8,PSW
|
|
|
; initialize TLB
|
; initialize TLB
|
mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries
|
mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries
|
add $8,$0,dmapaddr ; by impossible virtual page number
|
add $8,$0,dmapaddr ; by impossible virtual page number
|
mvts $8,TLB_ENTRY_HI
|
mvts $8,TLB_ENTRY_HI
|
add $8,$0,$0
|
add $8,$0,$0
|
add $9,$0,TLB_ENTRIES
|
add $9,$0,TLB_ENTRIES
|
tlbloop:
|
tlbloop:
|
mvts $8,TLB_INDEX
|
mvts $8,TLB_INDEX
|
tbwi
|
tbwi
|
add $8,$8,1
|
add $8,$8,1
|
bne $8,$9,tlbloop
|
bne $8,$9,tlbloop
|
|
|
; copy data segment
|
; copy data segment
|
add $10,$0,_bdata ; lowest dst addr to be written to
|
add $10,$0,_bdata ; lowest dst addr to be written to
|
add $8,$0,_edata ; one above the top dst addr
|
add $8,$0,_edata ; one above the top dst addr
|
sub $9,$8,$10 ; $9 = size of data segment
|
sub $9,$8,$10 ; $9 = size of data segment
|
add $9,$9,_ecode ; data is waiting right after code
|
add $9,$9,_ecode ; data is waiting right after code
|
j cpytest
|
j cpytest
|
cpyloop:
|
cpyloop:
|
ldw $11,$9,0 ; src addr in $9
|
ldw $11,$9,0 ; src addr in $9
|
stw $11,$8,0 ; dst addr in $8
|
stw $11,$8,0 ; dst addr in $8
|
cpytest:
|
cpytest:
|
sub $8,$8,4 ; downward
|
sub $8,$8,4 ; downward
|
sub $9,$9,4
|
sub $9,$9,4
|
bgeu $8,$10,cpyloop
|
bgeu $8,$10,cpyloop
|
|
|
; clear bss segment
|
; clear bss segment
|
add $8,$0,_bbss ; start with first word of bss
|
add $8,$0,_bbss ; start with first word of bss
|
add $9,$0,_ebss ; this is one above the top
|
add $9,$0,_ebss ; this is one above the top
|
j clrtest
|
j clrtest
|
clrloop:
|
clrloop:
|
stw $0,$8,0 ; dst addr in $8
|
stw $0,$8,0 ; dst addr in $8
|
add $8,$8,4 ; upward
|
add $8,$8,4 ; upward
|
clrtest:
|
clrtest:
|
bltu $8,$9,clrloop
|
bltu $8,$9,clrloop
|
|
|
; initialize I/O
|
; initialize I/O
|
add $29,$0,stacktop ; setup monitor stack
|
add $29,$0,stacktop ; setup monitor stack
|
jal kbdinit ; init keyboard
|
|
jal dspinit ; init display
|
|
jal ser0init ; init serial line 0
|
|
jal ser1init ; init serial line 1
|
|
jal dskinitctl ; init disk (controller)
|
|
jal dskinitser ; init disk (serial line)
|
|
ldw $8,$0,BIO_RD ; get switch settings
|
ldw $8,$0,BIO_RD ; get switch settings
|
and $8,$8,CIO_CTRL
|
and $8,$8,CIO_CTRL
|
add $4,$0,CIO_SERIAL_0 ; set console to serial line
|
add $4,$0,CIO_SERIAL_0 ; set console to serial line
|
bne $8,$0,swtchset
|
bne $8,$0,swtchset
|
add $4,$0,CIO_KBD_DSP ; set console to kbd/dsp
|
add $4,$0,CIO_KBD_DSP ; set console to kbd/dsp
|
swtchset:
|
swtchset:
|
jal setcio
|
jal setcio
|
|
ldbu $8,$0,cioctl ; get control byte
|
|
and $8,$8,0x01 ; keyboard input wanted?
|
|
bne $8,$0,nokbd ; no - then don't touch
|
|
jal kbdinit ; else init keyboard
|
|
nokbd:
|
|
ldbu $8,$0,cioctl ; get control byte
|
|
and $8,$8,0x02 ; display output wanted?
|
|
bne $8,$0,nodsp ; no - then don't touch
|
|
jal dspinit ; else init display
|
|
nodsp:
|
|
jal ser0init ; init serial line 0
|
|
jal ser1init ; init serial line 1
|
|
jal dskinitctl ; init disk (controller)
|
|
jal dskinitser ; init disk (serial line)
|
|
|
; call main
|
; call main
|
jal main ; enter command loop
|
jal main ; enter command loop
|
|
|
; main should never return
|
; main should never return
|
j start ; just to be sure...
|
j start ; just to be sure...
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
; Word getTLB_HI(int index)
|
; Word getTLB_HI(int index)
|
getTLB_HI:
|
getTLB_HI:
|
mvts $4,TLB_INDEX
|
mvts $4,TLB_INDEX
|
tbri
|
tbri
|
mvfs $2,TLB_ENTRY_HI
|
mvfs $2,TLB_ENTRY_HI
|
jr $31
|
jr $31
|
|
|
; Word getTLB_LO(int index)
|
; Word getTLB_LO(int index)
|
getTLB_LO:
|
getTLB_LO:
|
mvts $4,TLB_INDEX
|
mvts $4,TLB_INDEX
|
tbri
|
tbri
|
mvfs $2,TLB_ENTRY_LO
|
mvfs $2,TLB_ENTRY_LO
|
jr $31
|
jr $31
|
|
|
; void setTLB(int index, Word entryHi, Word entryLo)
|
; void setTLB(int index, Word entryHi, Word entryLo)
|
setTLB:
|
setTLB:
|
mvts $4,TLB_INDEX
|
mvts $4,TLB_INDEX
|
mvts $5,TLB_ENTRY_HI
|
mvts $5,TLB_ENTRY_HI
|
mvts $6,TLB_ENTRY_LO
|
mvts $6,TLB_ENTRY_LO
|
tbwi
|
tbwi
|
jr $31
|
jr $31
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.data
|
.data
|
.align 4
|
.align 4
|
|
|
cioctl:
|
cioctl:
|
.byte 0
|
.byte 0
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
; void setcon(Byte ctl)
|
; void setcon(Byte ctl)
|
setcio:
|
setcio:
|
stb $4,$0,cioctl
|
stb $4,$0,cioctl
|
j $31
|
j $31
|
|
|
; int cinchk(void)
|
; int cinchk(void)
|
cichk:
|
cichk:
|
ldbu $8,$0,cioctl
|
ldbu $8,$0,cioctl
|
and $8,$8,0x01
|
and $8,$8,0x01
|
bne $8,$0,cichk1
|
bne $8,$0,cichk1
|
j kbdinchk
|
j kbdinchk
|
cichk1:
|
cichk1:
|
j ser0inchk
|
j ser0inchk
|
|
|
; char cin(void)
|
; char cin(void)
|
ci:
|
ci:
|
ldbu $8,$0,cioctl
|
ldbu $8,$0,cioctl
|
and $8,$8,0x01
|
and $8,$8,0x01
|
bne $8,$0,ci1
|
bne $8,$0,ci1
|
j kbdin
|
j kbdin
|
ci1:
|
ci1:
|
j ser0in
|
j ser0in
|
|
|
; int coutchk(void)
|
; int coutchk(void)
|
cochk:
|
cochk:
|
ldbu $8,$0,cioctl
|
ldbu $8,$0,cioctl
|
and $8,$8,0x02
|
and $8,$8,0x02
|
bne $8,$0,cochk1
|
bne $8,$0,cochk1
|
j dspoutchk
|
j dspoutchk
|
cochk1:
|
cochk1:
|
j ser0outchk
|
j ser0outchk
|
|
|
; void cout(char c)
|
; void cout(char c)
|
co:
|
co:
|
ldbu $8,$0,cioctl
|
ldbu $8,$0,cioctl
|
and $8,$8,0x02
|
and $8,$8,0x02
|
bne $8,$0,co1
|
bne $8,$0,co1
|
j dspout
|
j dspout
|
co1:
|
co1:
|
j ser0out
|
j ser0out
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
; int dskcap(int dskno)
|
; int dskcap(int dskno)
|
dcap:
|
dcap:
|
bne $4,$0,dcapser
|
bne $4,$0,dcapser
|
j dskcapctl
|
j dskcapctl
|
dcapser:
|
dcapser:
|
j dskcapser
|
j dskcapser
|
|
|
; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
|
; int dskio(int dskno, char cmd, int sct, Word addr, int nscts)
|
dio:
|
dio:
|
bne $4,$0,dioser
|
bne $4,$0,dioser
|
add $4,$5,$0
|
add $4,$5,$0
|
add $5,$6,$0
|
add $5,$6,$0
|
add $6,$7,$0
|
add $6,$7,$0
|
ldw $7,$29,16
|
ldw $7,$29,16
|
j dskioctl
|
j dskioctl
|
dioser:
|
dioser:
|
add $4,$5,$0
|
add $4,$5,$0
|
add $5,$6,$0
|
add $5,$6,$0
|
add $6,$7,$0
|
add $6,$7,$0
|
ldw $7,$29,16
|
ldw $7,$29,16
|
j dskioser
|
j dskioser
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
; Bool saveState(MonitorState *msp)
|
; Bool saveState(MonitorState *msp)
|
; always return 'true' here
|
; always return 'true' here
|
saveState:
|
saveState:
|
stw $31,$4,0*4 ; return address
|
stw $31,$4,0*4 ; return address
|
stw $29,$4,1*4 ; stack pointer
|
stw $29,$4,1*4 ; stack pointer
|
stw $16,$4,2*4 ; local variables
|
stw $16,$4,2*4 ; local variables
|
stw $17,$4,3*4
|
stw $17,$4,3*4
|
stw $18,$4,4*4
|
stw $18,$4,4*4
|
stw $19,$4,5*4
|
stw $19,$4,5*4
|
stw $20,$4,6*4
|
stw $20,$4,6*4
|
stw $21,$4,7*4
|
stw $21,$4,7*4
|
stw $22,$4,8*4
|
stw $22,$4,8*4
|
stw $23,$4,9*4
|
stw $23,$4,9*4
|
add $2,$0,1
|
add $2,$0,1
|
jr $31
|
jr $31
|
|
|
; load state when re-entering monitor
|
; load state when re-entering monitor
|
; this appears as if returning from saveState
|
; this appears as if returning from saveState
|
; but the return value is 'false' here
|
; but the return value is 'false' here
|
loadState:
|
loadState:
|
ldw $8,$0,monitorReturn
|
ldw $8,$0,monitorReturn
|
beq $8,$0,loadState ; fatal error: monitor state lost
|
beq $8,$0,loadState ; fatal error: monitor state lost
|
ldw $31,$8,0*4 ; return address
|
ldw $31,$8,0*4 ; return address
|
ldw $29,$8,1*4 ; stack pointer
|
ldw $29,$8,1*4 ; stack pointer
|
ldw $16,$8,2*4 ; local variables
|
ldw $16,$8,2*4 ; local variables
|
ldw $17,$8,3*4
|
ldw $17,$8,3*4
|
ldw $18,$8,4*4
|
ldw $18,$8,4*4
|
ldw $19,$8,5*4
|
ldw $19,$8,5*4
|
ldw $20,$8,6*4
|
ldw $20,$8,6*4
|
ldw $21,$8,7*4
|
ldw $21,$8,7*4
|
ldw $22,$8,8*4
|
ldw $22,$8,8*4
|
ldw $23,$8,9*4
|
ldw $23,$8,9*4
|
add $2,$0,0
|
add $2,$0,0
|
jr $31
|
jr $31
|
|
|
.bss
|
.bss
|
.align 4
|
.align 4
|
|
|
; extern MonitorState *monitorReturn
|
; extern MonitorState *monitorReturn
|
monitorReturn:
|
monitorReturn:
|
.space 4
|
.space 4
|
|
|
; extern UserContext userContext
|
; extern UserContext userContext
|
userContext:
|
userContext:
|
.space USER_CONTEXT_SIZE
|
.space USER_CONTEXT_SIZE
|
|
|
;***************************************************************
|
;***************************************************************
|
|
|
.code
|
.code
|
.align 4
|
.align 4
|
|
|
; void resume(void)
|
; void resume(void)
|
; use userContext to load state
|
; use userContext to load state
|
resume:
|
resume:
|
mvts $0,PSW
|
mvts $0,PSW
|
add $24,$0,userContext
|
add $24,$0,userContext
|
.nosyn
|
.nosyn
|
ldw $8,$24,33*4 ; tlbIndex
|
ldw $8,$24,33*4 ; tlbIndex
|
mvts $8,TLB_INDEX
|
mvts $8,TLB_INDEX
|
ldw $8,$24,34*4 ; tlbEntryHi
|
ldw $8,$24,34*4 ; tlbEntryHi
|
mvts $8,TLB_ENTRY_HI
|
mvts $8,TLB_ENTRY_HI
|
ldw $8,$24,35*4 ; tlbEntryLo
|
ldw $8,$24,35*4 ; tlbEntryLo
|
mvts $8,TLB_ENTRY_LO
|
mvts $8,TLB_ENTRY_LO
|
ldw $8,$24,36*4 ; badAddress
|
ldw $8,$24,36*4 ; badAddress
|
mvts $8,BAD_ADDRESS
|
mvts $8,BAD_ADDRESS
|
ldw $8,$24,37*4 ; badAccess
|
ldw $8,$24,37*4 ; badAccess
|
mvts $8,BAD_ACCESS
|
mvts $8,BAD_ACCESS
|
;ldw $0,$24,0*4 ; registers
|
;ldw $0,$24,0*4 ; registers
|
ldw $1,$24,1*4
|
ldw $1,$24,1*4
|
ldw $2,$24,2*4
|
ldw $2,$24,2*4
|
ldw $3,$24,3*4
|
ldw $3,$24,3*4
|
ldw $4,$24,4*4
|
ldw $4,$24,4*4
|
ldw $5,$24,5*4
|
ldw $5,$24,5*4
|
ldw $6,$24,6*4
|
ldw $6,$24,6*4
|
ldw $7,$24,7*4
|
ldw $7,$24,7*4
|
ldw $8,$24,8*4
|
ldw $8,$24,8*4
|
ldw $9,$24,9*4
|
ldw $9,$24,9*4
|
ldw $10,$24,10*4
|
ldw $10,$24,10*4
|
ldw $11,$24,11*4
|
ldw $11,$24,11*4
|
ldw $12,$24,12*4
|
ldw $12,$24,12*4
|
ldw $13,$24,13*4
|
ldw $13,$24,13*4
|
ldw $14,$24,14*4
|
ldw $14,$24,14*4
|
ldw $15,$24,15*4
|
ldw $15,$24,15*4
|
ldw $16,$24,16*4
|
ldw $16,$24,16*4
|
ldw $17,$24,17*4
|
ldw $17,$24,17*4
|
ldw $18,$24,18*4
|
ldw $18,$24,18*4
|
ldw $19,$24,19*4
|
ldw $19,$24,19*4
|
ldw $20,$24,20*4
|
ldw $20,$24,20*4
|
ldw $21,$24,21*4
|
ldw $21,$24,21*4
|
ldw $22,$24,22*4
|
ldw $22,$24,22*4
|
ldw $23,$24,23*4
|
ldw $23,$24,23*4
|
;ldw $24,$24,24*4
|
;ldw $24,$24,24*4
|
ldw $25,$24,25*4
|
ldw $25,$24,25*4
|
ldw $26,$24,26*4
|
ldw $26,$24,26*4
|
ldw $27,$24,27*4
|
ldw $27,$24,27*4
|
ldw $28,$24,28*4
|
ldw $28,$24,28*4
|
ldw $29,$24,29*4
|
ldw $29,$24,29*4
|
ldw $30,$24,30*4
|
ldw $30,$24,30*4
|
ldw $31,$24,31*4
|
ldw $31,$24,31*4
|
ldw $24,$24,32*4 ; psw
|
ldw $24,$24,32*4 ; psw
|
mvts $24,PSW
|
mvts $24,PSW
|
rfx
|
rfx
|
.syn
|
.syn
|
|
|
; debug entry
|
; debug entry
|
; use userContext to store state
|
; use userContext to store state
|
debug:
|
debug:
|
.nosyn
|
.nosyn
|
ldhi $24,userContext
|
ldhi $24,userContext
|
or $24,$24,userContext
|
or $24,$24,userContext
|
stw $0,$24,0*4 ; registers
|
stw $0,$24,0*4 ; registers
|
stw $1,$24,1*4
|
stw $1,$24,1*4
|
stw $2,$24,2*4
|
stw $2,$24,2*4
|
stw $3,$24,3*4
|
stw $3,$24,3*4
|
stw $4,$24,4*4
|
stw $4,$24,4*4
|
stw $5,$24,5*4
|
stw $5,$24,5*4
|
stw $6,$24,6*4
|
stw $6,$24,6*4
|
stw $7,$24,7*4
|
stw $7,$24,7*4
|
stw $8,$24,8*4
|
stw $8,$24,8*4
|
stw $9,$24,9*4
|
stw $9,$24,9*4
|
stw $10,$24,10*4
|
stw $10,$24,10*4
|
stw $11,$24,11*4
|
stw $11,$24,11*4
|
stw $12,$24,12*4
|
stw $12,$24,12*4
|
stw $13,$24,13*4
|
stw $13,$24,13*4
|
stw $14,$24,14*4
|
stw $14,$24,14*4
|
stw $15,$24,15*4
|
stw $15,$24,15*4
|
stw $16,$24,16*4
|
stw $16,$24,16*4
|
stw $17,$24,17*4
|
stw $17,$24,17*4
|
stw $18,$24,18*4
|
stw $18,$24,18*4
|
stw $19,$24,19*4
|
stw $19,$24,19*4
|
stw $20,$24,20*4
|
stw $20,$24,20*4
|
stw $21,$24,21*4
|
stw $21,$24,21*4
|
stw $22,$24,22*4
|
stw $22,$24,22*4
|
stw $23,$24,23*4
|
stw $23,$24,23*4
|
stw $24,$24,24*4
|
stw $24,$24,24*4
|
stw $25,$24,25*4
|
stw $25,$24,25*4
|
stw $26,$24,26*4
|
stw $26,$24,26*4
|
stw $27,$24,27*4
|
stw $27,$24,27*4
|
stw $28,$24,28*4
|
stw $28,$24,28*4
|
stw $29,$24,29*4
|
stw $29,$24,29*4
|
stw $30,$24,30*4
|
stw $30,$24,30*4
|
stw $31,$24,31*4
|
stw $31,$24,31*4
|
mvfs $8,PSW
|
mvfs $8,PSW
|
stw $8,$24,32*4 ; psw
|
stw $8,$24,32*4 ; psw
|
mvfs $8,TLB_INDEX
|
mvfs $8,TLB_INDEX
|
stw $8,$24,33*4 ; tlbIndex
|
stw $8,$24,33*4 ; tlbIndex
|
mvfs $8,TLB_ENTRY_HI
|
mvfs $8,TLB_ENTRY_HI
|
stw $8,$24,34*4 ; tlbEntryHi
|
stw $8,$24,34*4 ; tlbEntryHi
|
mvfs $8,TLB_ENTRY_LO
|
mvfs $8,TLB_ENTRY_LO
|
stw $8,$24,35*4 ; tlbEntryLo
|
stw $8,$24,35*4 ; tlbEntryLo
|
mvfs $8,BAD_ADDRESS
|
mvfs $8,BAD_ADDRESS
|
stw $8,$24,36*4 ; badAddress
|
stw $8,$24,36*4 ; badAddress
|
mvfs $8,BAD_ACCESS
|
mvfs $8,BAD_ACCESS
|
stw $8,$24,37*4 ; badAccess
|
stw $8,$24,37*4 ; badAccess
|
.syn
|
.syn
|
j loadState
|
j loadState
|
|
|
