/*
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/*
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* cpu.c -- CPU simulation
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* cpu.c -- CPU simulation
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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#include <setjmp.h>
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#include <setjmp.h>
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#include "common.h"
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#include "common.h"
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#include "console.h"
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#include "console.h"
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#include "error.h"
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#include "error.h"
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#include "except.h"
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#include "except.h"
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#include "instr.h"
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#include "instr.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "mmu.h"
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#include "timer.h"
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#include "timer.h"
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/**************************************************************/
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/**************************************************************/
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#define RR(n) r[n]
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#define RR(n) r[n]
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#define WR(n,d) ((void) ((n) != 0 ? r[n] = (d) : (d)))
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#define WR(n,d) ((void) ((n) != 0 ? r[n] = (d) : (d)))
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#define V (psw & PSW_V)
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#define V (psw & PSW_V)
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#define UM (psw & PSW_UM)
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#define UM (psw & PSW_UM)
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#define PUM (psw & PSW_PUM)
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#define PUM (psw & PSW_PUM)
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#define OUM (psw & PSW_OUM)
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#define OUM (psw & PSW_OUM)
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#define IE (psw & PSW_IE)
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#define IE (psw & PSW_IE)
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#define PIE (psw & PSW_PIE)
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#define PIE (psw & PSW_PIE)
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#define OIE (psw & PSW_OIE)
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#define OIE (psw & PSW_OIE)
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/**************************************************************/
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/**************************************************************/
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static Bool debugIRQ = false; /* set to true if debugging IRQs */
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static Bool debugIRQ = false; /* set to true if debugging IRQs */
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static Word pc; /* program counter */
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static Word pc; /* program counter */
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static Word psw; /* processor status word */
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static Word psw; /* processor status word */
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static Word r[32]; /* general purpose registers */
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static Word r[32]; /* general purpose registers */
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static unsigned irqPending; /* one bit for each pending IRQ */
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static unsigned irqPending; /* one bit for each pending IRQ */
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static Bool breakSet; /* breakpoint set if true */
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static Bool breakSet; /* breakpoint set if true */
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static Word breakAddr; /* if breakSet, this is where */
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static Word breakAddr; /* if breakSet, this is where */
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static Word total; /* counts total number of instrs */
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static Word total; /* counts total number of instrs */
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static Bool run; /* CPU runs continuously if true */
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static Bool run; /* CPU runs continuously if true */
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static Word startAddr; /* start of ROM (or start of RAM, */
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static Word startAddr; /* start of ROM (or start of RAM, */
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/* in case a program was loaded) */
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/* in case a program was loaded) */
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/**************************************************************/
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/**************************************************************/
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static void handleInterrupts(void) {
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static void handleInterrupts(void) {
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unsigned irqMask;
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unsigned irqMask;
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unsigned irqSeen;
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unsigned irqSeen;
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int priority;
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int priority;
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/* handle exceptions and interrupts */
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/* handle exceptions and interrupts */
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if (irqPending == 0) {
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if (irqPending == 0) {
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/* no exception or interrupt pending */
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/* no exception or interrupt pending */
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return;
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return;
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}
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}
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/* at least one exception or interrupt is pending */
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/* at least one exception or interrupt is pending */
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irqMask = ~PSW_IRQ_MASK | (psw & PSW_IRQ_MASK);
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irqMask = ~PSW_IRQ_MASK | (psw & PSW_IRQ_MASK);
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if (debugIRQ) {
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if (debugIRQ) {
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cPrintf("**** IRQ = 0x%08X ****\n", irqPending);
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cPrintf("**** IRQ = 0x%08X ****\n", irqPending);
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cPrintf("**** MASK = 0x%08X ****\n", irqMask);
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cPrintf("**** MASK = 0x%08X ****\n", irqMask);
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}
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}
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irqSeen = irqPending & irqMask;
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irqSeen = irqPending & irqMask;
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if (irqSeen == 0) {
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if (irqSeen == 0) {
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/* none that gets through */
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/* none that gets through */
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return;
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return;
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}
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}
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/* determine the one with the highest priority */
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/* determine the one with the highest priority */
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for (priority = 31; priority >= 0; priority--) {
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for (priority = 31; priority >= 0; priority--) {
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if ((irqSeen & ((unsigned) 1 << priority)) != 0) {
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if ((irqSeen & ((unsigned) 1 << priority)) != 0) {
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/* highest priority among visible ones found */
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/* highest priority among visible ones found */
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break;
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break;
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}
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}
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}
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}
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/* acknowledge exception, or interrupt if enabled */
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/* acknowledge exception, or interrupt if enabled */
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if (priority >= 16 || IE != 0) {
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if (priority >= 16 || IE != 0) {
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if (priority >= 16) {
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if (priority >= 16) {
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/* clear corresponding bit in irqPending vector */
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/* clear corresponding bit in irqPending vector */
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/* only done for exceptions, since interrupts are level-sensitive */
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/* only done for exceptions, since interrupts are level-sensitive */
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irqPending &= ~((unsigned) 1 << priority);
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irqPending &= ~((unsigned) 1 << priority);
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}
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}
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/* copy and reset interrupt enable bit in PSW */
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/* copy and reset interrupt enable bit in PSW */
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if (PIE != 0) {
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if (PIE != 0) {
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psw |= PSW_OIE;
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psw |= PSW_OIE;
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} else {
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} else {
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psw &= ~PSW_OIE;
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psw &= ~PSW_OIE;
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}
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}
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if (IE != 0) {
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if (IE != 0) {
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psw |= PSW_PIE;
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psw |= PSW_PIE;
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} else {
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} else {
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psw &= ~PSW_PIE;
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psw &= ~PSW_PIE;
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}
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}
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psw &= ~PSW_IE;
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psw &= ~PSW_IE;
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/* copy and reset user mode enable bit in PSW */
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/* copy and reset user mode enable bit in PSW */
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if (PUM != 0) {
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if (PUM != 0) {
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psw |= PSW_OUM;
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psw |= PSW_OUM;
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} else {
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} else {
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psw &= ~PSW_OUM;
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psw &= ~PSW_OUM;
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}
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}
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if (UM != 0) {
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if (UM != 0) {
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psw |= PSW_PUM;
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psw |= PSW_PUM;
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} else {
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} else {
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psw &= ~PSW_PUM;
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psw &= ~PSW_PUM;
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}
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}
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psw &= ~PSW_UM;
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psw &= ~PSW_UM;
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/* reflect priority in PSW */
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/* reflect priority in PSW */
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psw &= ~PSW_PRIO_MASK;
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psw &= ~PSW_PRIO_MASK;
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psw |= priority << PSW_PRIO_SHFT;
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psw |= priority << PSW_PRIO_SHFT;
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/* save interrupt return address and start service routine */
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/* save interrupt return address and start service routine */
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WR(30, pc);
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WR(30, pc);
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if (V == 0) {
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if (V == 0) {
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/* exceptions and interrupts are vectored to ROM */
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/* exceptions and interrupts are vectored to ROM */
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pc = 0xC0000000 | ROM_BASE;
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pc = 0xC0000000 | ROM_BASE;
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} else {
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} else {
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/* exceptions and interrupts are vectored to RAM */
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/* exceptions and interrupts are vectored to RAM */
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pc = 0xC0000000;
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pc = 0xC0000000;
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}
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}
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if (priority == EXC_TLB_MISS &&
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if (priority == EXC_TLB_MISS &&
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(mmuGetBadAddr() & 0x80000000) == 0) {
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(mmuGetBadAddr() & 0x80000000) == 0) {
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/* user TLB miss exception */
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/* user TLB miss exception */
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pc |= 0x00000008;
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pc |= 0x00000008;
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} else {
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} else {
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/* any other exception or interrupt */
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/* any other exception or interrupt */
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pc |= 0x00000004;
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pc |= 0x00000004;
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}
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}
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}
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}
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}
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}
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static void execNextInstruction(void) {
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static void execNextInstruction(void) {
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Word instr;
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Word instr;
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Word next;
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Word next;
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int op, reg1, reg2, reg3;
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int op, reg1, reg2, reg3;
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Half immed;
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Half immed;
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Word offset;
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Word offset;
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int scnt;
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int scnt;
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Word smsk;
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Word smsk;
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Word aux;
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Word aux;
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/* count the instruction */
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/* count the instruction */
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total++;
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total++;
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/* fetch the instruction */
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/* fetch the instruction */
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instr = mmuReadWord(pc, UM);
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instr = mmuReadWord(pc, UM);
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/* decode the instruction */
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/* decode the instruction */
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op = (instr >> 26) & 0x3F;
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op = (instr >> 26) & 0x3F;
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reg1 = (instr >> 21) & 0x1F;
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reg1 = (instr >> 21) & 0x1F;
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reg2 = (instr >> 16) & 0x1F;
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reg2 = (instr >> 16) & 0x1F;
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reg3 = (instr >> 11) & 0x1F;
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reg3 = (instr >> 11) & 0x1F;
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immed = instr & 0x0000FFFF;
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immed = instr & 0x0000FFFF;
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offset = instr & 0x03FFFFFF;
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offset = instr & 0x03FFFFFF;
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next = pc + 4;
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next = pc + 4;
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/* execute the instruction */
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/* execute the instruction */
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switch (op) {
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switch (op) {
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case OP_ADD:
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case OP_ADD:
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WR(reg3, (signed int) RR(reg1) + (signed int) RR(reg2));
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WR(reg3, (signed int) RR(reg1) + (signed int) RR(reg2));
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break;
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break;
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case OP_ADDI:
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case OP_ADDI:
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WR(reg2, (signed int) RR(reg1) + (signed int) SEXT16(immed));
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WR(reg2, (signed int) RR(reg1) + (signed int) SEXT16(immed));
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break;
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break;
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case OP_SUB:
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case OP_SUB:
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WR(reg3, (signed int) RR(reg1) - (signed int) RR(reg2));
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WR(reg3, (signed int) RR(reg1) - (signed int) RR(reg2));
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break;
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break;
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case OP_SUBI:
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case OP_SUBI:
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WR(reg2, (signed int) RR(reg1) - (signed int) SEXT16(immed));
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WR(reg2, (signed int) RR(reg1) - (signed int) SEXT16(immed));
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break;
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break;
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case OP_MUL:
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case OP_MUL:
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WR(reg3, (signed int) RR(reg1) * (signed int) RR(reg2));
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WR(reg3, (signed int) RR(reg1) * (signed int) RR(reg2));
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break;
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break;
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case OP_MULI:
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case OP_MULI:
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WR(reg2, (signed int) RR(reg1) * (signed int) SEXT16(immed));
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WR(reg2, (signed int) RR(reg1) * (signed int) SEXT16(immed));
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break;
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break;
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case OP_MULU:
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case OP_MULU:
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WR(reg3, RR(reg1) * RR(reg2));
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WR(reg3, RR(reg1) * RR(reg2));
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break;
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break;
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case OP_MULUI:
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case OP_MULUI:
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WR(reg2, RR(reg1) * ZEXT16(immed));
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WR(reg2, RR(reg1) * ZEXT16(immed));
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break;
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break;
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case OP_DIV:
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case OP_DIV:
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if (RR(reg2) == 0) {
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if (RR(reg2) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg3, (signed int) RR(reg1) / (signed int) RR(reg2));
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WR(reg3, (signed int) RR(reg1) / (signed int) RR(reg2));
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break;
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break;
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case OP_DIVI:
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case OP_DIVI:
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if (SEXT16(immed) == 0) {
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if (SEXT16(immed) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg2, (signed int) RR(reg1) / (signed int) SEXT16(immed));
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WR(reg2, (signed int) RR(reg1) / (signed int) SEXT16(immed));
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break;
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break;
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case OP_DIVU:
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case OP_DIVU:
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if (RR(reg2) == 0) {
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if (RR(reg2) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg3, RR(reg1) / RR(reg2));
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WR(reg3, RR(reg1) / RR(reg2));
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break;
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break;
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case OP_DIVUI:
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case OP_DIVUI:
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if (SEXT16(immed) == 0) {
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if (SEXT16(immed) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg2, RR(reg1) / ZEXT16(immed));
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WR(reg2, RR(reg1) / ZEXT16(immed));
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break;
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break;
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case OP_REM:
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case OP_REM:
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if (RR(reg2) == 0) {
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if (RR(reg2) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg3, (signed int) RR(reg1) % (signed int) RR(reg2));
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WR(reg3, (signed int) RR(reg1) % (signed int) RR(reg2));
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break;
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break;
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case OP_REMI:
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case OP_REMI:
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if (SEXT16(immed) == 0) {
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if (SEXT16(immed) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg2, (signed int) RR(reg1) % (signed int) SEXT16(immed));
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WR(reg2, (signed int) RR(reg1) % (signed int) SEXT16(immed));
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break;
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break;
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case OP_REMU:
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case OP_REMU:
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if (RR(reg2) == 0) {
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if (RR(reg2) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg3, RR(reg1) % RR(reg2));
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WR(reg3, RR(reg1) % RR(reg2));
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break;
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break;
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case OP_REMUI:
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case OP_REMUI:
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if (SEXT16(immed) == 0) {
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if (SEXT16(immed) == 0) {
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throwException(EXC_DIVIDE);
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throwException(EXC_DIVIDE);
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}
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}
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WR(reg2, RR(reg1) % ZEXT16(immed));
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WR(reg2, RR(reg1) % ZEXT16(immed));
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break;
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break;
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case OP_AND:
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case OP_AND:
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WR(reg3, RR(reg1) & RR(reg2));
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WR(reg3, RR(reg1) & RR(reg2));
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break;
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break;
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case OP_ANDI:
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case OP_ANDI:
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WR(reg2, RR(reg1) & ZEXT16(immed));
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WR(reg2, RR(reg1) & ZEXT16(immed));
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break;
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break;
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case OP_OR:
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case OP_OR:
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WR(reg3, RR(reg1) | RR(reg2));
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WR(reg3, RR(reg1) | RR(reg2));
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break;
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break;
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case OP_ORI:
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case OP_ORI:
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WR(reg2, RR(reg1) | ZEXT16(immed));
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WR(reg2, RR(reg1) | ZEXT16(immed));
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break;
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break;
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case OP_XOR:
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case OP_XOR:
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WR(reg3, RR(reg1) ^ RR(reg2));
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WR(reg3, RR(reg1) ^ RR(reg2));
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break;
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break;
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case OP_XORI:
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case OP_XORI:
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WR(reg2, RR(reg1) ^ ZEXT16(immed));
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WR(reg2, RR(reg1) ^ ZEXT16(immed));
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break;
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break;
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case OP_XNOR:
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case OP_XNOR:
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WR(reg3, ~(RR(reg1) ^ RR(reg2)));
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WR(reg3, ~(RR(reg1) ^ RR(reg2)));
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break;
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break;
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case OP_XNORI:
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case OP_XNORI:
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WR(reg2, ~(RR(reg1) ^ ZEXT16(immed)));
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WR(reg2, ~(RR(reg1) ^ ZEXT16(immed)));
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break;
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break;
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case OP_SLL:
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case OP_SLL:
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scnt = RR(reg2) & 0x1F;
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scnt = RR(reg2) & 0x1F;
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WR(reg3, RR(reg1) << scnt);
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WR(reg3, RR(reg1) << scnt);
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break;
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break;
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case OP_SLLI:
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case OP_SLLI:
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scnt = immed & 0x1F;
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scnt = immed & 0x1F;
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WR(reg2, RR(reg1) << scnt);
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WR(reg2, RR(reg1) << scnt);
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break;
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break;
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case OP_SLR:
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case OP_SLR:
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scnt = RR(reg2) & 0x1F;
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scnt = RR(reg2) & 0x1F;
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WR(reg3, RR(reg1) >> scnt);
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WR(reg3, RR(reg1) >> scnt);
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break;
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break;
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case OP_SLRI:
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case OP_SLRI:
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scnt = immed & 0x1F;
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scnt = immed & 0x1F;
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WR(reg2, RR(reg1) >> scnt);
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WR(reg2, RR(reg1) >> scnt);
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break;
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break;
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case OP_SAR:
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case OP_SAR:
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scnt = RR(reg2) & 0x1F;
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scnt = RR(reg2) & 0x1F;
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smsk = (RR(reg1) & 0x80000000 ? ~(((Word) 0xFFFFFFFF) >> scnt) : 0);
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smsk = (RR(reg1) & 0x80000000 ? ~(((Word) 0xFFFFFFFF) >> scnt) : 0);
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WR(reg3, smsk | (RR(reg1) >> scnt));
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WR(reg3, smsk | (RR(reg1) >> scnt));
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break;
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break;
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case OP_SARI:
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case OP_SARI:
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scnt = immed & 0x1F;
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scnt = immed & 0x1F;
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smsk = (RR(reg1) & 0x80000000 ? ~(((Word) 0xFFFFFFFF) >> scnt) : 0);
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smsk = (RR(reg1) & 0x80000000 ? ~(((Word) 0xFFFFFFFF) >> scnt) : 0);
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WR(reg2, smsk | (RR(reg1) >> scnt));
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WR(reg2, smsk | (RR(reg1) >> scnt));
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break;
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break;
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case OP_LDHI:
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case OP_LDHI:
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WR(reg2, ZEXT16(immed) << 16);
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WR(reg2, ZEXT16(immed) << 16);
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break;
|
break;
|
case OP_BEQ:
|
case OP_BEQ:
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if (RR(reg1) == RR(reg2)) {
|
if (RR(reg1) == RR(reg2)) {
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next += SEXT16(immed) << 2;
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next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BNE:
|
case OP_BNE:
|
if (RR(reg1) != RR(reg2)) {
|
if (RR(reg1) != RR(reg2)) {
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next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BLE:
|
case OP_BLE:
|
if ((signed int) RR(reg1) <= (signed int) RR(reg2)) {
|
if ((signed int) RR(reg1) <= (signed int) RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BLEU:
|
case OP_BLEU:
|
if (RR(reg1) <= RR(reg2)) {
|
if (RR(reg1) <= RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BLT:
|
case OP_BLT:
|
if ((signed int) RR(reg1) < (signed int) RR(reg2)) {
|
if ((signed int) RR(reg1) < (signed int) RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BLTU:
|
case OP_BLTU:
|
if (RR(reg1) < RR(reg2)) {
|
if (RR(reg1) < RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BGE:
|
case OP_BGE:
|
if ((signed int) RR(reg1) >= (signed int) RR(reg2)) {
|
if ((signed int) RR(reg1) >= (signed int) RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BGEU:
|
case OP_BGEU:
|
if (RR(reg1) >= RR(reg2)) {
|
if (RR(reg1) >= RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BGT:
|
case OP_BGT:
|
if ((signed int) RR(reg1) > (signed int) RR(reg2)) {
|
if ((signed int) RR(reg1) > (signed int) RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_BGTU:
|
case OP_BGTU:
|
if (RR(reg1) > RR(reg2)) {
|
if (RR(reg1) > RR(reg2)) {
|
next += SEXT16(immed) << 2;
|
next += SEXT16(immed) << 2;
|
}
|
}
|
break;
|
break;
|
case OP_J:
|
case OP_J:
|
next += SEXT26(offset) << 2;
|
next += SEXT26(offset) << 2;
|
break;
|
break;
|
case OP_JR:
|
case OP_JR:
|
next = RR(reg1);
|
next = RR(reg1);
|
break;
|
break;
|
case OP_JAL:
|
case OP_JAL:
|
WR(31, next);
|
WR(31, next);
|
next += SEXT26(offset) << 2;
|
next += SEXT26(offset) << 2;
|
break;
|
break;
|
case OP_JALR:
|
case OP_JALR:
|
aux = RR(reg1);
|
aux = RR(reg1);
|
WR(31, next);
|
WR(31, next);
|
next = aux;
|
next = aux;
|
break;
|
break;
|
case OP_TRAP:
|
case OP_TRAP:
|
throwException(EXC_TRAP);
|
throwException(EXC_TRAP);
|
break;
|
break;
|
case OP_RFX:
|
case OP_RFX:
|
if (UM != 0) {
|
if (UM != 0) {
|
throwException(EXC_PRV_INSTRCT);
|
throwException(EXC_PRV_INSTRCT);
|
}
|
}
|
if (PIE != 0) {
|
if (PIE != 0) {
|
psw |= PSW_IE;
|
psw |= PSW_IE;
|
} else {
|
} else {
|
psw &= ~PSW_IE;
|
psw &= ~PSW_IE;
|
}
|
}
|
if (OIE != 0) {
|
if (OIE != 0) {
|
psw |= PSW_PIE;
|
psw |= PSW_PIE;
|
} else {
|
} else {
|
psw &= ~PSW_PIE;
|
psw &= ~PSW_PIE;
|
}
|
}
|
if (PUM != 0) {
|
if (PUM != 0) {
|
psw |= PSW_UM;
|
psw |= PSW_UM;
|
} else {
|
} else {
|
psw &= ~PSW_UM;
|
psw &= ~PSW_UM;
|
}
|
}
|
if (OUM != 0) {
|
if (OUM != 0) {
|
psw |= PSW_PUM;
|
psw |= PSW_PUM;
|
} else {
|
} else {
|
psw &= ~PSW_PUM;
|
psw &= ~PSW_PUM;
|
}
|
}
|
next = RR(30);
|
next = RR(30);
|
break;
|
break;
|
case OP_LDW:
|
case OP_LDW:
|
WR(reg2, mmuReadWord(RR(reg1) + SEXT16(immed), UM));
|
WR(reg2, mmuReadWord(RR(reg1) + SEXT16(immed), UM));
|
break;
|
break;
|
case OP_LDH:
|
case OP_LDH:
|
WR(reg2, (signed int) (signed short)
|
WR(reg2, (signed int) (signed short)
|
mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
|
mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
|
break;
|
break;
|
case OP_LDHU:
|
case OP_LDHU:
|
WR(reg2, mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
|
WR(reg2, mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
|
break;
|
break;
|
case OP_LDB:
|
case OP_LDB:
|
WR(reg2, (signed int) (signed char)
|
WR(reg2, (signed int) (signed char)
|
mmuReadByte(RR(reg1) + SEXT16(immed), UM));
|
mmuReadByte(RR(reg1) + SEXT16(immed), UM));
|
break;
|
break;
|
case OP_LDBU:
|
case OP_LDBU:
|
WR(reg2, mmuReadByte(RR(reg1) + SEXT16(immed), UM));
|
WR(reg2, mmuReadByte(RR(reg1) + SEXT16(immed), UM));
|
break;
|
break;
|
case OP_STW:
|
case OP_STW:
|
mmuWriteWord(RR(reg1) + SEXT16(immed), RR(reg2), UM);
|
mmuWriteWord(RR(reg1) + SEXT16(immed), RR(reg2), UM);
|
break;
|
break;
|
case OP_STH:
|
case OP_STH:
|
mmuWriteHalf(RR(reg1) + SEXT16(immed), RR(reg2), UM);
|
mmuWriteHalf(RR(reg1) + SEXT16(immed), RR(reg2), UM);
|
break;
|
break;
|
case OP_STB:
|
case OP_STB:
|
mmuWriteByte(RR(reg1) + SEXT16(immed), RR(reg2), UM);
|
mmuWriteByte(RR(reg1) + SEXT16(immed), RR(reg2), UM);
|
break;
|
break;
|
case OP_MVFS:
|
case OP_MVFS:
|
switch (immed) {
|
switch (immed) {
|
case 0:
|
case 0:
|
WR(reg2, psw);
|
WR(reg2, psw);
|
break;
|
break;
|
case 1:
|
case 1:
|
WR(reg2, mmuGetIndex());
|
WR(reg2, mmuGetIndex());
|
break;
|
break;
|
case 2:
|
case 2:
|
WR(reg2, mmuGetEntryHi());
|
WR(reg2, mmuGetEntryHi());
|
break;
|
break;
|
case 3:
|
case 3:
|
WR(reg2, mmuGetEntryLo());
|
WR(reg2, mmuGetEntryLo());
|
break;
|
break;
|
case 4:
|
case 4:
|
WR(reg2, mmuGetBadAddr());
|
WR(reg2, mmuGetBadAddr());
|
break;
|
break;
|
|
case 5:
|
|
WR(reg2, mmuGetBadAccs());
|
|
break;
|
default:
|
default:
|
throwException(EXC_ILL_INSTRCT);
|
throwException(EXC_ILL_INSTRCT);
|
break;
|
break;
|
}
|
}
|
break;
|
break;
|
case OP_MVTS:
|
case OP_MVTS:
|
if (UM != 0) {
|
if (UM != 0) {
|
throwException(EXC_PRV_INSTRCT);
|
throwException(EXC_PRV_INSTRCT);
|
}
|
}
|
switch (immed) {
|
switch (immed) {
|
case 0:
|
case 0:
|
psw = RR(reg2);
|
psw = RR(reg2);
|
break;
|
break;
|
case 1:
|
case 1:
|
mmuSetIndex(RR(reg2));
|
mmuSetIndex(RR(reg2));
|
break;
|
break;
|
case 2:
|
case 2:
|
mmuSetEntryHi(RR(reg2));
|
mmuSetEntryHi(RR(reg2));
|
break;
|
break;
|
case 3:
|
case 3:
|
mmuSetEntryLo(RR(reg2));
|
mmuSetEntryLo(RR(reg2));
|
break;
|
break;
|
case 4:
|
case 4:
|
mmuSetBadAddr(RR(reg2));
|
mmuSetBadAddr(RR(reg2));
|
break;
|
break;
|
|
case 5:
|
|
mmuSetBadAccs(RR(reg2));
|
|
break;
|
default:
|
default:
|
throwException(EXC_ILL_INSTRCT);
|
throwException(EXC_ILL_INSTRCT);
|
break;
|
break;
|
}
|
}
|
break;
|
break;
|
case OP_TBS:
|
case OP_TBS:
|
if (UM != 0) {
|
if (UM != 0) {
|
throwException(EXC_PRV_INSTRCT);
|
throwException(EXC_PRV_INSTRCT);
|
}
|
}
|
mmuTbs();
|
mmuTbs();
|
break;
|
break;
|
case OP_TBWR:
|
case OP_TBWR:
|
if (UM != 0) {
|
if (UM != 0) {
|
throwException(EXC_PRV_INSTRCT);
|
throwException(EXC_PRV_INSTRCT);
|
}
|
}
|
mmuTbwr();
|
mmuTbwr();
|
break;
|
break;
|
case OP_TBRI:
|
case OP_TBRI:
|
if (UM != 0) {
|
if (UM != 0) {
|
throwException(EXC_PRV_INSTRCT);
|
throwException(EXC_PRV_INSTRCT);
|
}
|
}
|
mmuTbri();
|
mmuTbri();
|
break;
|
break;
|
case OP_TBWI:
|
case OP_TBWI:
|
if (UM != 0) {
|
if (UM != 0) {
|
throwException(EXC_PRV_INSTRCT);
|
throwException(EXC_PRV_INSTRCT);
|
}
|
}
|
mmuTbwi();
|
mmuTbwi();
|
break;
|
break;
|
default:
|
default:
|
throwException(EXC_ILL_INSTRCT);
|
throwException(EXC_ILL_INSTRCT);
|
break;
|
break;
|
}
|
}
|
/* update PC */
|
/* update PC */
|
pc = next;
|
pc = next;
|
}
|
}
|
|
|
|
|
/**************************************************************/
|
/**************************************************************/
|
|
|
|
|
Word cpuGetPC(void) {
|
Word cpuGetPC(void) {
|
return pc;
|
return pc;
|
}
|
}
|
|
|
|
|
void cpuSetPC(Word addr) {
|
void cpuSetPC(Word addr) {
|
pc = addr;
|
pc = addr;
|
}
|
}
|
|
|
|
|
Word cpuGetReg(int regnum) {
|
Word cpuGetReg(int regnum) {
|
return RR(regnum & 0x1F);
|
return RR(regnum & 0x1F);
|
}
|
}
|
|
|
|
|
void cpuSetReg(int regnum, Word value) {
|
void cpuSetReg(int regnum, Word value) {
|
WR(regnum & 0x1F, value);
|
WR(regnum & 0x1F, value);
|
}
|
}
|
|
|
|
|
Word cpuGetPSW(void) {
|
Word cpuGetPSW(void) {
|
return psw;
|
return psw;
|
}
|
}
|
|
|
|
|
void cpuSetPSW(Word value) {
|
void cpuSetPSW(Word value) {
|
psw = value;
|
psw = value;
|
}
|
}
|
|
|
|
|
Word cpuGetIRQ(void) {
|
Word cpuGetIRQ(void) {
|
return irqPending;
|
return irqPending;
|
}
|
}
|
|
|
|
|
Bool cpuTestBreak(void) {
|
Bool cpuTestBreak(void) {
|
return breakSet;
|
return breakSet;
|
}
|
}
|
|
|
|
|
Word cpuGetBreak(void) {
|
Word cpuGetBreak(void) {
|
return breakAddr;
|
return breakAddr;
|
}
|
}
|
|
|
|
|
void cpuSetBreak(Word addr) {
|
void cpuSetBreak(Word addr) {
|
breakAddr = addr;
|
breakAddr = addr;
|
breakSet = true;
|
breakSet = true;
|
}
|
}
|
|
|
|
|
void cpuResetBreak(void) {
|
void cpuResetBreak(void) {
|
breakSet = false;
|
breakSet = false;
|
}
|
}
|
|
|
|
|
Word cpuGetTotal(void) {
|
Word cpuGetTotal(void) {
|
return total;
|
return total;
|
}
|
}
|
|
|
|
|
void cpuStep(void) {
|
void cpuStep(void) {
|
jmp_buf myEnvironment;
|
jmp_buf myEnvironment;
|
int exception;
|
int exception;
|
|
|
exception = setjmp(myEnvironment);
|
exception = setjmp(myEnvironment);
|
if (exception == 0) {
|
if (exception == 0) {
|
/* initialization */
|
/* initialization */
|
pushEnvironment(&myEnvironment);
|
pushEnvironment(&myEnvironment);
|
timerTick();
|
timerTick();
|
execNextInstruction();
|
execNextInstruction();
|
handleInterrupts();
|
handleInterrupts();
|
} else {
|
} else {
|
/* an exception was thrown */
|
/* an exception was thrown */
|
cpuSetInterrupt(exception);
|
cpuSetInterrupt(exception);
|
handleInterrupts();
|
handleInterrupts();
|
}
|
}
|
popEnvironment();
|
popEnvironment();
|
}
|
}
|
|
|
|
|
void cpuRun(void) {
|
void cpuRun(void) {
|
jmp_buf myEnvironment;
|
jmp_buf myEnvironment;
|
int exception;
|
int exception;
|
|
|
run = true;
|
run = true;
|
exception = setjmp(myEnvironment);
|
exception = setjmp(myEnvironment);
|
if (exception == 0) {
|
if (exception == 0) {
|
/* initialization */
|
/* initialization */
|
pushEnvironment(&myEnvironment);
|
pushEnvironment(&myEnvironment);
|
} else {
|
} else {
|
/* an exception was thrown */
|
/* an exception was thrown */
|
cpuSetInterrupt(exception);
|
cpuSetInterrupt(exception);
|
handleInterrupts();
|
handleInterrupts();
|
if (breakSet && pc == breakAddr) {
|
if (breakSet && pc == breakAddr) {
|
run = false;
|
run = false;
|
}
|
}
|
}
|
}
|
while (run) {
|
while (run) {
|
timerTick();
|
timerTick();
|
execNextInstruction();
|
execNextInstruction();
|
handleInterrupts();
|
handleInterrupts();
|
if (breakSet && pc == breakAddr) {
|
if (breakSet && pc == breakAddr) {
|
run = false;
|
run = false;
|
}
|
}
|
}
|
}
|
popEnvironment();
|
popEnvironment();
|
}
|
}
|
|
|
|
|
void cpuHalt(void) {
|
void cpuHalt(void) {
|
run = false;
|
run = false;
|
}
|
}
|
|
|
|
|
void cpuSetInterrupt(int priority) {
|
void cpuSetInterrupt(int priority) {
|
irqPending |= ((unsigned) 1 << priority);
|
irqPending |= ((unsigned) 1 << priority);
|
}
|
}
|
|
|
|
|
void cpuResetInterrupt(int priority) {
|
void cpuResetInterrupt(int priority) {
|
irqPending &= ~((unsigned) 1 << priority);
|
irqPending &= ~((unsigned) 1 << priority);
|
}
|
}
|
|
|
|
|
void cpuReset(void) {
|
void cpuReset(void) {
|
int i;
|
int i;
|
|
|
cPrintf("Resetting CPU...\n");
|
cPrintf("Resetting CPU...\n");
|
/* most registers are in a random state */
|
/* most registers are in a random state */
|
for (i = 1; i < 32; i++) {
|
for (i = 1; i < 32; i++) {
|
r[i] = rand();
|
r[i] = rand();
|
}
|
}
|
/* but not all */
|
/* but not all */
|
pc = startAddr;
|
pc = startAddr;
|
r[0] = 0;
|
r[0] = 0;
|
psw = 0;
|
psw = 0;
|
/* reset simulator control variables */
|
/* reset simulator control variables */
|
irqPending = 0;
|
irqPending = 0;
|
total = 0;
|
total = 0;
|
}
|
}
|
|
|
|
|
void cpuInit(Word initialPC) {
|
void cpuInit(Word initialPC) {
|
startAddr = initialPC;
|
startAddr = initialPC;
|
cpuReset();
|
cpuReset();
|
}
|
}
|
|
|
|
|
void cpuExit(void) {
|
void cpuExit(void) {
|
}
|
}
|
|
|
