OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [sim/] [cpu.h] - Diff between revs 8 and 25

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 8 Rev 25
/*
/*
 * cpu.h -- CPU simulation
 * cpu.h -- CPU simulation
 */
 */
 
 
 
 
#ifndef _CPU_H_
#ifndef _CPU_H_
#define _CPU_H_
#define _CPU_H_
 
 
 
 
#define IRQ_TIMER       14              /* timer interrupt */
#define IRQ_TIMER_1     15              /* timer 1 interrupt */
 
#define IRQ_TIMER_0     14              /* timer 0 interrupt */
#define IRQ_DISK        8               /* disk interrupt */
#define IRQ_DISK        8               /* disk interrupt */
#define IRQ_KEYBOARD    4               /* keyboard interrupt */
#define IRQ_KEYBOARD    4               /* keyboard interrupt */
#define IRQ_TERM_1_RCVR 3               /* terminal 1 receiver interrupt */
#define IRQ_TERM_1_RCVR 3               /* terminal 1 receiver interrupt */
#define IRQ_TERM_1_XMTR 2               /* terminal 1 transmitter interrupt */
#define IRQ_TERM_1_XMTR 2               /* terminal 1 transmitter interrupt */
#define IRQ_TERM_0_RCVR 1               /* terminal 0 receiver interrupt */
#define IRQ_TERM_0_RCVR 1               /* terminal 0 receiver interrupt */
#define IRQ_TERM_0_XMTR 0                /* terminal 0 transmitter interrupt */
#define IRQ_TERM_0_XMTR 0                /* terminal 0 transmitter interrupt */
 
 
#define PSW_V           0x08000000      /* interrupt vector bit in PSW */
#define PSW_V           0x08000000      /* interrupt vector bit in PSW */
#define PSW_UM          0x04000000      /* user mode enable bit in PSW */
#define PSW_UM          0x04000000      /* user mode enable bit in PSW */
#define PSW_PUM         0x02000000      /* previous value of PSW_UM */
#define PSW_PUM         0x02000000      /* previous value of PSW_UM */
#define PSW_OUM         0x01000000      /* old value of PSW_UM */
#define PSW_OUM         0x01000000      /* old value of PSW_UM */
#define PSW_IE          0x00800000      /* interrupt enable bit in PSW */
#define PSW_IE          0x00800000      /* interrupt enable bit in PSW */
#define PSW_PIE         0x00400000      /* previous value of PSW_IE */
#define PSW_PIE         0x00400000      /* previous value of PSW_IE */
#define PSW_OIE         0x00200000      /* old value of PSW_IE */
#define PSW_OIE         0x00200000      /* old value of PSW_IE */
#define PSW_PRIO_MASK   0x001F0000      /* bits to encode IRQ prio in PSW */
#define PSW_PRIO_MASK   0x001F0000      /* bits to encode IRQ prio in PSW */
#define PSW_PRIO_SHFT   16              /* shift count to reach these bits */
#define PSW_PRIO_SHFT   16              /* shift count to reach these bits */
#define PSW_IRQ_MASK    0x0000FFFF      /* IRQ mask bits */
#define PSW_IRQ_MASK    0x0000FFFF      /* IRQ mask bits */
 
 
 
 
Word cpuGetPC(void);
Word cpuGetPC(void);
void cpuSetPC(Word addr);
void cpuSetPC(Word addr);
 
 
Word cpuGetReg(int regnum);
Word cpuGetReg(int regnum);
void cpuSetReg(int regnum, Word value);
void cpuSetReg(int regnum, Word value);
 
 
Word cpuGetPSW(void);
Word cpuGetPSW(void);
void cpuSetPSW(Word value);
void cpuSetPSW(Word value);
 
 
Word cpuGetIRQ(void);
Word cpuGetIRQ(void);
 
 
Bool cpuTestBreak(void);
Bool cpuTestBreak(void);
Word cpuGetBreak(void);
Word cpuGetBreak(void);
void cpuSetBreak(Word addr);
void cpuSetBreak(Word addr);
void cpuResetBreak(void);
void cpuResetBreak(void);
 
 
Word cpuGetTotal(void);
Word cpuGetTotal(void);
 
 
void cpuStep(void);
void cpuStep(void);
void cpuRun(void);
void cpuRun(void);
void cpuHalt(void);
void cpuHalt(void);
 
 
void cpuSetInterrupt(int priority);
void cpuSetInterrupt(int priority);
void cpuResetInterrupt(int priority);
void cpuResetInterrupt(int priority);
 
 
void cpuReset(void);
void cpuReset(void);
void cpuInit(Word initialPC);
void cpuInit(Word initialPC);
void cpuExit(void);
void cpuExit(void);
 
 
 
 
#endif /* _CPU_H_ */
#endif /* _CPU_H_ */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.