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[/] [eco32/] [trunk/] [sim/] [mmu.h] - Diff between revs 8 and 168

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Rev 8 Rev 168
/*
/*
 * mmu.h -- MMU simulation
 * mmu.h -- MMU simulation
 */
 */
 
 
 
 
#ifndef _MMU_H_
#ifndef _MMU_H_
#define _MMU_H_
#define _MMU_H_
 
 
 
 
#define TLB_SHFT        5               /* log2 of number of TLB entries */
#define TLB_SHFT        5               /* log2 of number of TLB entries */
#define TLB_SIZE        (1 << TLB_SHFT) /* total number of TLB entries */
#define TLB_SIZE        (1 << TLB_SHFT) /* total number of TLB entries */
#define TLB_MASK        (TLB_SIZE - 1)  /* mask for number of TLB entries */
#define TLB_MASK        (TLB_SIZE - 1)  /* mask for number of TLB entries */
#define TLB_FIXED       4               /* number of fixed TLB entries */
#define TLB_FIXED       4               /* number of fixed TLB entries */
 
 
#define TLB_WRITE       (1 << 1)        /* write bit in EntryLo */
#define TLB_WRITE       (1 << 1)        /* write bit in EntryLo */
#define TLB_VALID       (1 << 0)        /* valid bit in EntryLo */
#define TLB_VALID       (1 << 0)        /* valid bit in EntryLo */
 
 
 
#define MMU_ACCS_MASK   0x07            /* bits used in BadAccs */
 
#define MMU_ACCS_READ   0x00            /* access type = read */
 
#define MMU_ACCS_WRITE  0x04            /* access type = write */
 
#define MMU_ACCS_BYTE   0x00            /* access width = byte */
 
#define MMU_ACCS_HALF   0x01            /* access width = half */
 
#define MMU_ACCS_WORD   0x02            /* access width = word */
 
 
 
 
typedef struct {
typedef struct {
  Word page;            /* 20 high-order bits of virtual address */
  Word page;            /* 20 high-order bits of virtual address */
  Word frame;           /* 20 high-order bits of physical address */
  Word frame;           /* 20 high-order bits of physical address */
  Bool write;           /* must be true to allow writing to the page */
  Bool write;           /* must be true to allow writing to the page */
  Bool valid;           /* must be true for the entry to be valid */
  Bool valid;           /* must be true for the entry to be valid */
} TLB_Entry;
} TLB_Entry;
 
 
 
 
Word mmuReadWord(Word vAddr, Bool userMode);
Word mmuReadWord(Word vAddr, Bool userMode);
Half mmuReadHalf(Word vAddr, Bool userMode);
Half mmuReadHalf(Word vAddr, Bool userMode);
Byte mmuReadByte(Word vAddr, Bool userMode);
Byte mmuReadByte(Word vAddr, Bool userMode);
void mmuWriteWord(Word vAddr, Word data, Bool userMode);
void mmuWriteWord(Word vAddr, Word data, Bool userMode);
void mmuWriteHalf(Word vAddr, Half data, Bool userMode);
void mmuWriteHalf(Word vAddr, Half data, Bool userMode);
void mmuWriteByte(Word vAddr, Byte data, Bool userMode);
void mmuWriteByte(Word vAddr, Byte data, Bool userMode);
 
 
Word mmuGetIndex(void);
Word mmuGetIndex(void);
void mmuSetIndex(Word value);
void mmuSetIndex(Word value);
Word mmuGetEntryHi(void);
Word mmuGetEntryHi(void);
void mmuSetEntryHi(Word value);
void mmuSetEntryHi(Word value);
Word mmuGetEntryLo(void);
Word mmuGetEntryLo(void);
void mmuSetEntryLo(Word value);
void mmuSetEntryLo(Word value);
Word mmuGetBadAddr(void);
Word mmuGetBadAddr(void);
void mmuSetBadAddr(Word value);
void mmuSetBadAddr(Word value);
 
Word mmuGetBadAccs(void);
 
void mmuSetBadAccs(Word value);
 
 
void mmuTbs(void);
void mmuTbs(void);
void mmuTbwr(void);
void mmuTbwr(void);
void mmuTbri(void);
void mmuTbri(void);
void mmuTbwi(void);
void mmuTbwi(void);
 
 
TLB_Entry mmuGetTLB(int index);
TLB_Entry mmuGetTLB(int index);
void mmuSetTLB(int index, TLB_Entry tlbEntry);
void mmuSetTLB(int index, TLB_Entry tlbEntry);
 
 
void mmuReset(void);
void mmuReset(void);
void mmuInit(void);
void mmuInit(void);
void mmuExit(void);
void mmuExit(void);
 
 
 
 
#endif /* _MMU_H_ */
#endif /* _MMU_H_ */
 
 

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