# ECPU 0.1.alpha
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# ECPU 0.1.alpha
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# ==============
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# ==============
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#
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#
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# Background
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# Background
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# ========
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# ========
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# Resurrected university project originally written in VHDL.
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# Resurrected university project originally written in VHDL.
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# Converted to Verilog by hand and fixed bugs.
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# Converted to Verilog by hand and fixed bugs.
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#
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#
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# Modifications made in verilog post-conversion:
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# Modifications made in verilog post-conversion:
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# - New barrel shifter
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# - New barrel shifter
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# - Reviewed opcode list
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# - Reviewed opcode list
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# - Enhanced testbench to allow for random stimulus (verilog only tb)
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# - Enhanced testbench to allow for random stimulus (verilog only tb)
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# - Tested using Icarus
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# - Tested using Icarus
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#
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#
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# Currently checking for synthesis:
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# Currently checking for synthesis:
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# - Passes synthesis checks using "veriwell ... +synopsys"
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# - Passes synthesis checks using "veriwell ... +synopsys"
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#
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#
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# Features
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# Features
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# ========
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# ========
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# * 15 working opcodes/functions :
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# * 15 working opcodes/functions :
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# cADD_AB
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# cADD_AB
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# cINC_A
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# cINC_A
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# cINC_B
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# cINC_B
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# cSUB_AB
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# cSUB_AB
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# cCMP_AB - Same as Xor
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# cCMP_AB - Same as Xor
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# cASL_AbyB - Uses last three bits of B (barrel shift)
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# cASL_AbyB - Uses last three bits of B (barrel shift)
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# cASR_AbyB - Uses last three bits of B (barrel shift)
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# cASR_AbyB - Uses last three bits of B (barrel shift)
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# cCLR - Clear outputs
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# cCLR - Clear outputs
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# cDEC_A
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# cDEC_A
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# cDEC_B
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# cDEC_B
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# cMUL_AB - not implemented [yet]
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# cMUL_AB - not implemented [yet]
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# cCPL_A
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# cCPL_A
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# cAND_AB
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# cAND_AB
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# cOR_AB
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# cOR_AB
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# cXOR_AB
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# cXOR_AB
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# cCPL_B
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# cCPL_B
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#
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#
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# * Flags C, V, Z - not implemented [yet]
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# * Flags C, V, Z - not implemented [yet]
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#
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#
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# C - TBD
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# C - TBD
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# V - TBD
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# V - TBD
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# Z - TBD
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# Z - TBD
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#
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#
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# Simulating
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# Simulating
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# ========
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# ========
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#
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#
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# 1) Run the setup.sh script
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# 1) Run the setup.sh script in the top level directory
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# ./setup.sh
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# source ./setup.sh
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#
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#
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# 2) Modify sim/alu_test.txt as required (or leave as is for first time demo)
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# 2) Modify sim/alu_test.txt as required (or leave as is for first time demo)
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#
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#
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# 3) Execute the run script (from the sim directory)
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# 3) Execute the run script (from the sim directory)
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#
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#
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# unix_prompt% cd sim
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# unix_prompt% cd sim
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# unix_prompt% ./runit [options]
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# unix_prompt% ./runit [options]
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#
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#
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#
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#
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# Available options:
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# Available options:
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#
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#
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# * Any valid iverilog option
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# * Any valid iverilog option
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#
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#
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# * Use -D and the following defines to modify testbench behaviour
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# * Use -D and the following defines to modify testbench behaviour
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#
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#
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#
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#
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# DECIMAL_DISPLAY Display information in decimal
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# DECIMAL_DISPLAY Display information in decimal
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# HEX_DISPLAY Display information in hex
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# HEX_DISPLAY Display information in hex
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# BINARY_DISPLAY Display information in binary
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# BINARY_DISPLAY Display information in binary
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#
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#
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# RANDOM= Ignore alu_test.txt and generate
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# RANDOM= Ignore alu_test.txt and generate
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# $random stimulus.
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# $random stimulus.
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#
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#
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# DEBUG_ALU_TB Print out extra information for debug
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# DEBUG_ALU_TB Print out extra information for debug
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#
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#
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# FORCE_A= Force ALU input A to a constant value
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# FORCE_A= Force ALU input A to a constant value
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# FORCE_B= Force ALU input B to a constant value
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# FORCE_B= Force ALU input B to a constant value
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# FORCE_OPCODE= Force ALU input S to a constant string
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# FORCE_OPCODE= Force ALU input S to a constant string
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# FORCE_CLR= Force ALU input CLR to a constant bit
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# FORCE_CLR= Force ALU input CLR to a constant bit
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#
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#
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# STOP_ON_ERROR Stop on the first error encountered
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# STOP_ON_ERROR Stop on the first error encountered
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#
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#
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# CREATE_SIGNAL_LOG Create a log file containing IO states per
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# CREATE_SIGNAL_LOG Create a log file containing IO states per
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# posedge clk
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# posedge clk
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#
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#
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#
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#
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# example:
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# example:
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# % ./runit -DRANDOM=10000 -DSTOP_ON_ERROR &> log
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# % ./runit -DRANDOM=10000 -DSTOP_ON_ERROR &> log
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#
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#
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#
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#
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