library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.fpmult_comp.all;
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use work.fpmult_comp.all;
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use work.fpmult_stage_pre_comp.all;
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use work.fpmult_stage0_comp.all;
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use work.fpmult_stage0_comp.all;
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use work.fpmult_stageN_comp.all;
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use work.fpmult_stageN_comp.all;
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use work.fpmult_stage23_comp.all;
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use work.fpmult_stage23_comp.all;
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entity fpmult is
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entity fpmult is
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port(
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port(
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clk:in std_logic;
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clk:in std_logic;
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d:in fpmult_in_type;
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d:in fpmult_in_type;
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q:out fpmult_out_type
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q:out fpmult_out_type
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);
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);
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end;
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end;
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architecture structural of fpmult is
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architecture structural of fpmult is
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signal fpmult_stage_pre_in:fpmult_stage_pre_in_type;
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signal fpmult_stage_pre_out:fpmult_stage_pre_out_type;
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signal fpmult_stage0_in:fpmult_stage0_in_type;
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signal fpmult_stage0_in:fpmult_stage0_in_type;
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signal fpmult_stage0_out:fpmult_stage0_out_type;
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signal fpmult_stage0_out:fpmult_stage0_out_type;
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signal fpmult_stage23_in:fpmult_stage23_in_type;
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signal fpmult_stage23_in:fpmult_stage23_in_type;
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signal fpmult_stage23_out:fpmult_stage23_out_type;
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signal fpmult_stage23_out:fpmult_stage23_out_type;
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type fpmult_stageN_in_array_type is array(23 downto 1) of fpmult_stageN_in_type;
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type fpmult_stageN_in_array_type is array(23 downto 1) of fpmult_stageN_in_type;
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type fpmult_stageN_out_array_type is array(22 downto 1) of fpmult_stageN_out_type;
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type fpmult_stageN_out_array_type is array(22 downto 1) of fpmult_stageN_out_type;
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signal fpmult_stageN_in_array:fpmult_stageN_in_array_type;
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signal fpmult_stageN_in_array:fpmult_stageN_in_array_type;
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signal fpmult_stageN_out_array:fpmult_stageN_out_array_type;
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signal fpmult_stageN_out_array:fpmult_stageN_out_array_type;
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begin
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begin
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fpmult_stage0_in.a<=d.a;
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fpmult_stage_pre_in.a<=d.a;
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fpmult_stage0_in.b<=d.b;
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fpmult_stage_pre_in.b<=d.b;
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stage_pre:fpmult_stage_pre port map(clk,fpmult_stage_pre_in,fpmult_stage_pre_out);
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fpmult_stage0_in.a<=fpmult_stage_pre_out.a;
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fpmult_stage0_in.b<=fpmult_stage_pre_out.b;
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stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
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stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
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fpmult_stageN_in_array(1)<=fpmult_stage0_out;
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fpmult_stageN_in_array(1)<=fpmult_stage0_out;
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pipeline:for N in 22 downto 1 generate
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pipeline:for N in 22 downto 1 generate
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stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
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stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
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fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
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fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
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end generate pipeline;
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end generate pipeline;
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fpmult_stage23_in<=fpmult_stageN_out_array(22);
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fpmult_stage23_in<=fpmult_stageN_out_array(22);
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stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
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stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
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q.p<=fpmult_stage23_out.p;
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q.p<=fpmult_stage23_out.p;
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end;
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end;
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