library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.fp_generic.all;
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use work.fp_generic.all;
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use work.fpmult_stage0_comp.all;
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use work.fpmult_stage0_comp.all;
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entity fpmult_stage0 is
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entity fpmult_stage0 is
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port(
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port(
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clk:in std_logic;
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clk:in std_logic;
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d:in fpmult_stage0_in_type;
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d:in fpmult_stage0_in_type;
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q:out fpmult_stage0_out_type
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q:out fpmult_stage0_out_type
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);
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);
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end;
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end;
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architecture twoproc of fpmult_stage0 is
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architecture twoproc of fpmult_stage0 is
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type reg_type is record
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type reg_type is record
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a:fp_type;
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a:fp_type;
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b:fp_type;
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b:fp_type;
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p_sign:fp_sign_type;
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p_sign:fp_sign_type;
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p_exp:fp_exp_type;
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p_exp:fp_exp_type;
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p_mantissa:fp_long_mantissa_type;
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p_mantissa:fp_long_mantissa_type;
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end record;
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end record;
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signal r,rin:reg_type;
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signal r,rin:reg_type;
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begin
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begin
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comb:process(d,r)
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comb:process(d,r)
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variable v:reg_type;
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variable v:reg_type;
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variable a_is_normal,b_is_normal:boolean;
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variable a_is_subnormal,b_is_subnormal:boolean;
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variable a_is_zero,b_is_zero:boolean;
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variable a_is_infinite,b_is_infinite:boolean;
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variable a_is_nan,b_is_nan:boolean;
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variable is_normal:boolean;
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variable is_zero:boolean;
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variable is_infinite:boolean;
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variable is_nan:boolean;
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begin
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begin
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-- sample register outputs
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-- sample register outputs
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v:=r;
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v:=r;
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-- overload
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-- overload
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v.a:=d.a;
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v.a:=d.a;
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v.b:=d.b;
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v.b:=d.b;
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a_is_normal:=fp_is_normal(v.a);
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b_is_normal:=fp_is_normal(v.b);
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a_is_subnormal:=fp_is_subnormal(v.a);
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b_is_subnormal:=fp_is_subnormal(v.b);
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a_is_zero:=fp_is_zero(v.a);
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b_is_zero:=fp_is_zero(v.b);
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a_is_infinite:=fp_is_infinite(v.a);
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b_is_infinite:=fp_is_infinite(v.b);
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a_is_nan:=fp_is_nan(v.a);
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b_is_nan:=fp_is_nan(v.b);
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if a_is_normal or b_is_normal then
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if a_is_normal and b_is_normal then
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is_normal:=true;
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end if;
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if a_is_zero or b_is_zero then
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is_zero:=true;
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end if;
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if a_is_infinite or b_is_infinite then
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is_infinite:=true;
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end if;
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if a_is_nan or b_is_nan then
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is_nan:=true;
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end if;
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end if;
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v.p_sign:=fp_sign(d.a) xor fp_sign(d.b);
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v.p_sign:=fp_sign(d.a) xor fp_sign(d.b);
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v.p_exp:=fp_exp(d.a) + fp_exp(d.b) - 127;
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v.p_exp:=fp_exp(d.a) + fp_exp(d.b) - 127;
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if fp_mantissa(d.b)(0)='1' then
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if fp_mantissa(d.b)(0)='1' then
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v.p_mantissa:=resize(fp_mantissa(d.a),48);
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v.p_mantissa:=resize(fp_mantissa(d.a),48);
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else
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else
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v.p_mantissa:=(others=>'0');
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v.p_mantissa:=(others=>'0');
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end if;
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end if;
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-- drive register inputs
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-- drive register inputs
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rin<=v;
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rin<=v;
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-- drive outputs
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-- drive outputs
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q.a<=r.a;
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q.a<=r.a;
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q.b<=r.b;
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q.b<=r.b;
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q.p_sign<=r.p_sign;
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q.p_sign<=r.p_sign;
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q.p_exp<=r.p_exp;
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q.p_exp<=r.p_exp;
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q.p_mantissa<=r.p_mantissa;
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q.p_mantissa<=r.p_mantissa;
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end process;
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end process;
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seq:process(clk,rin)
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seq:process(clk,rin)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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r<=rin;
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r<=rin;
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end if;
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end if;
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end process;
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end process;
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