-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Politecnico di Torino
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-- Politecnico di Torino
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-- Dipartimento di Automatica e Informatica
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-- Dipartimento di Automatica e Informatica
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : Simple Counter with clear
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-- Title : Simple Counter with clear
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--
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--
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-- File name : counterclear.vhd
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-- File name : counterclear.vhd
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--
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--
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-- Description : Counter with clear.
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-- Description : Counter with clear.
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--
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--
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-- Authors : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>
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-- Authors : Erwing R. Sanchez <erwing.sanchez@polito.it>
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--
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-- Rev. History : 22 july 06
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity COUNTERCLR is
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entity COUNTERCLR is
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generic (
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generic (
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width : integer := 8);
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width : integer := 8);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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en : in std_logic;
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en : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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outcnt : out std_logic_vector(width-1 downto 0));
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outcnt : out std_logic_vector(width-1 downto 0));
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end COUNTERCLR;
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end COUNTERCLR;
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architecture COUNTERCLR1 of COUNTERCLR is
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architecture COUNTERCLR1 of COUNTERCLR is
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signal cnt : std_logic_vector(width-1 downto 0);
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signal cnt : std_logic_vector(width-1 downto 0);
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begin -- COUNTERCLR1
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begin -- COUNTERCLR1
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process (clk, rst_n)
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process (clk, rst_n)
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begin -- process
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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cnt <= (others => '0');
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cnt <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if en = '1' then
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if en = '1' then
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cnt <= conv_std_logic_vector(CONV_INTEGER(cnt) + 1, width);
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cnt <= conv_std_logic_vector(CONV_INTEGER(cnt) + 1, width);
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elsif clear = '1' then
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elsif clear = '1' then
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cnt <= (others => '0');
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cnt <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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outcnt <= cnt;
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outcnt <= cnt;
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end COUNTERCLR1;
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end COUNTERCLR1;
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