-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Politecnico di Torino
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-- Politecnico di Torino
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-- Dipartimento di Automatica e Informatica
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-- Dipartimento di Automatica e Informatica
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : EPC Class1 Gen2 RFID Tag - CRC5 encoder/decoder
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-- Title : EPC Class1 Gen2 RFID Tag - CRC5 encoder/decoder
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--
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--
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-- File name : crc5encdec.vhd
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-- File name : crc5encdec.vhd
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--
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--
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-- Description : Tag CRC5 encoder/decoder
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-- Description : Tag CRC5 encoder/decoder
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--
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--
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-- Authors : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>
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-- Authors : Erwing R. Sanchez <erwing.sanchez@polito.it>
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--
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-- Rev. History : 10 July 06
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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entity crc5encdec is
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entity crc5encdec is
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generic(
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generic(
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PRESET_CRC5 : integer := 9); -- "01001"
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PRESET_CRC5 : integer := 9); -- "01001"
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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init : in std_logic;
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init : in std_logic;
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ce : in std_logic;
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ce : in std_logic;
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sdi : in std_logic;
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sdi : in std_logic;
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cout : out std_logic_vector(4 downto 0));
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cout : out std_logic_vector(4 downto 0));
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end crc5encdec;
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end crc5encdec;
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architecture CRC5beh of crc5encdec is
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architecture CRC5beh of crc5encdec is
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signal crc5reg : std_logic_vector(4 downto 0);
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signal crc5reg : std_logic_vector(4 downto 0);
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begin -- CRC5beh
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begin -- CRC5beh
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process (clk, rst_n)
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process (clk, rst_n)
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begin -- process
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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crc5reg <= (others => '0');
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crc5reg <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if init = '1' then
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if init = '1' then
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crc5reg <= conv_std_logic_vector(PRESET_CRC5,5);
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crc5reg <= conv_std_logic_vector(PRESET_CRC5,5);
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elsif ce = '1' then
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elsif ce = '1' then
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crc5reg(0) <= crc5reg(4) xor sdi;
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crc5reg(0) <= crc5reg(4) xor sdi;
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crc5reg(2 downto 1) <= crc5reg(1 downto 0);
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crc5reg(2 downto 1) <= crc5reg(1 downto 0);
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crc5reg(3) <= crc5reg(4) xor sdi xor crc5reg(2);
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crc5reg(3) <= crc5reg(4) xor sdi xor crc5reg(2);
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crc5reg(4) <= crc5reg(3);
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crc5reg(4) <= crc5reg(3);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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cout <= crc5reg;
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cout <= crc5reg;
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end CRC5beh;
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end CRC5beh;
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