-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Politecnico di Torino
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-- Politecnico di Torino
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-- Dipartimento di Automatica e Informatica
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-- Dipartimento di Automatica e Informatica
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : Memory Controller
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-- Title : Memory Controller
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--
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--
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-- File name : MemCtrl.vhd
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-- File name : MemCtrl.vhd
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--
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--
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-- Description : Flash memory controller.
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-- Description : Flash memory controller.
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--
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--
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-- Authors : Erwing Sanchez <erwing.sanchezsanchez@polito.it>
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-- Authors : Erwing Sanchez <erwing.sanchez@polito.it>
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--
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-- Rev. History : Erwing Sanchez -- 17/07/06
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- EPC Memory Map
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-- EPC Memory Map
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--
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--
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-- _______________________
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-- _______________________
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-- | | RESERVED MEMORY (Bank 00)
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-- | | RESERVED MEMORY (Bank 00)
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-- | |
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-- | |
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-- |_______________________|
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-- |_______________________|
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-- | | EPC MEMORY (Bank 01)
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-- | | EPC MEMORY (Bank 01)
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-- | |
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-- | |
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-- |_______________________|
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-- |_______________________|
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-- | | TID MEMORY (Bank 10)
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-- | | TID MEMORY (Bank 10)
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-- | |
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-- | |
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-- |_______________________|
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-- |_______________________|
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-- | | USER MEMORY (Bank 11)
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-- | | USER MEMORY (Bank 11)
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-- | |
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-- | |
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-- |_______________________|
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-- |_______________________|
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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|
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entity Mem_ctrl is
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entity Mem_ctrl is
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generic (
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generic (
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WordsRSV : integer := 8;
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WordsRSV : integer := 8;
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WordsEPC : integer := 16;
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WordsEPC : integer := 16;
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WordsTID : integer := 8;
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WordsTID : integer := 8;
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WordsUSR : integer := 256;
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WordsUSR : integer := 256;
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--Address are loaded in two steps, so only half of address pins are needed.
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--Address are loaded in two steps, so only half of address pins are needed.
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AddrRSV : integer := 2; -- 1/2address pins
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AddrRSV : integer := 2; -- 1/2address pins
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AddrEPC : integer := 3; -- 1/2address pins
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AddrEPC : integer := 3; -- 1/2address pins
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AddrTID : integer := 2; -- 1/2address pins
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AddrTID : integer := 2; -- 1/2address pins
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AddrUSR : integer := 5; -- 1/2address pins
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AddrUSR : integer := 5; -- 1/2address pins
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Data : integer := 16);
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Data : integer := 16);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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BANK : in std_logic_vector(1 downto 0);
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BANK : in std_logic_vector(1 downto 0);
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WR : in std_logic; -- Write signal
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WR : in std_logic; -- Write signal
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RD : in std_logic; -- Read signal
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RD : in std_logic; -- Read signal
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ADR : in std_logic_vector((2*AddrUSR)-1 downto 0);
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ADR : in std_logic_vector((2*AddrUSR)-1 downto 0);
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DTI : in std_logic_vector(Data-1 downto 0);
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DTI : in std_logic_vector(Data-1 downto 0);
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DTO : out std_logic_vector(Data-1 downto 0);
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DTO : out std_logic_vector(Data-1 downto 0);
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RB : out std_logic -- Ready/nBusy signal(unbuffered!)
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RB : out std_logic -- Ready/nBusy signal(unbuffered!)
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);
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);
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end Mem_ctrl;
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end Mem_ctrl;
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architecture Mem_Ctrl_arch of Mem_ctrl is
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architecture Mem_Ctrl_arch of Mem_ctrl is
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component Flash_MeM_EPC
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component Flash_MeM_EPC
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generic (
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generic (
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Words : integer;
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Words : integer;
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Addr : integer;
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Addr : integer;
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Data : integer);
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Data : integer);
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port (
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port (
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A : in std_logic_vector(Addr-1 downto 0);
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A : in std_logic_vector(Addr-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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G : in std_logic;
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G : in std_logic;
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W : in std_logic;
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W : in std_logic;
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RC : in std_logic;
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RC : in std_logic;
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st : out std_logic);
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st : out std_logic);
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end component;
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end component;
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component Flash_MeM_TID
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component Flash_MeM_TID
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generic (
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generic (
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Words : integer;
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Words : integer;
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Addr : integer;
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Addr : integer;
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Data : integer);
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Data : integer);
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port (
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port (
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A : in std_logic_vector(Addr-1 downto 0);
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A : in std_logic_vector(Addr-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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G : in std_logic;
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G : in std_logic;
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W : in std_logic;
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W : in std_logic;
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RC : in std_logic;
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RC : in std_logic;
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st : out std_logic);
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st : out std_logic);
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end component;
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end component;
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component Flash_MeM_USR
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component Flash_MeM_USR
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generic (
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generic (
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Words : integer;
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Words : integer;
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Addr : integer;
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Addr : integer;
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Data : integer);
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Data : integer);
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port (
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port (
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A : in std_logic_vector(Addr-1 downto 0);
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A : in std_logic_vector(Addr-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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G : in std_logic;
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G : in std_logic;
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W : in std_logic;
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W : in std_logic;
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RC : in std_logic;
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RC : in std_logic;
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st : out std_logic);
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st : out std_logic);
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end component;
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end component;
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component Flash_MeM_RSV
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component Flash_MeM_RSV
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generic (
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generic (
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Words : integer;
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Words : integer;
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Addr : integer;
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Addr : integer;
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Data : integer);
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Data : integer);
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port (
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port (
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A : in std_logic_vector(Addr-1 downto 0);
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A : in std_logic_vector(Addr-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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D : in std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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Q : out std_logic_vector(Data-1 downto 0);
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G : in std_logic;
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G : in std_logic;
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W : in std_logic;
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W : in std_logic;
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RC : in std_logic;
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RC : in std_logic;
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st : out std_logic);
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st : out std_logic);
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end component;
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end component;
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-- Contants
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-- Contants
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constant WriteCommand : std_logic_vector(Data-1 downto 0) := conv_std_logic_vector(64, Data); --"01000000" Flash Write Code
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constant WriteCommand : std_logic_vector(Data-1 downto 0) := conv_std_logic_vector(64, Data); --"01000000" Flash Write Code
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-- FSM
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-- FSM
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type MemCtrl_t is (st_idle, st_read_LoadAddr1, st_read_LoadAddr2, st_read_LoadOutput, st_read_read, st_write_LoadAddr1, st_write_LoadAddr2, st_write_write);
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type MemCtrl_t is (st_idle, st_read_LoadAddr1, st_read_LoadAddr2, st_read_LoadOutput, st_read_read, st_write_LoadAddr1, st_write_LoadAddr2, st_write_write);
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signal StMCtrl, NextStMCtrl : MemCtrl_t;
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signal StMCtrl, NextStMCtrl : MemCtrl_t;
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-- Memory signals
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-- Memory signals
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signal A_RSV : std_logic_vector(AddrRSV-1 downto 0);
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signal A_RSV : std_logic_vector(AddrRSV-1 downto 0);
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signal A_EPC : std_logic_vector(AddrEPC-1 downto 0);
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signal A_EPC : std_logic_vector(AddrEPC-1 downto 0);
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signal A_TID : std_logic_vector(AddrTID-1 downto 0);
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signal A_TID : std_logic_vector(AddrTID-1 downto 0);
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signal A_USR : std_logic_vector(AddrUSR-1 downto 0);
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signal A_USR : std_logic_vector(AddrUSR-1 downto 0);
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signal D : std_logic_vector(Data-1 downto 0);
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signal D : std_logic_vector(Data-1 downto 0);
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signal Q : std_logic_vector(Data-1 downto 0);
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signal Q : std_logic_vector(Data-1 downto 0);
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signal G, G_i : std_logic;
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signal G, G_i : std_logic;
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signal W, W_i : std_logic;
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signal W, W_i : std_logic;
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signal RC, RC_i : std_logic;
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signal RC, RC_i : std_logic;
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signal st : std_logic;
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signal st : std_logic;
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signal W_RSV, W_EPC, W_TID, W_USR : std_logic;
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signal W_RSV, W_EPC, W_TID, W_USR : std_logic;
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signal G_RSV, G_EPC, G_TID, G_USR : std_logic;
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signal G_RSV, G_EPC, G_TID, G_USR : std_logic;
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signal Q_RSV, Q_EPC, Q_TID, Q_USR : std_logic_vector(Data-1 downto 0);
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signal Q_RSV, Q_EPC, Q_TID, Q_USR : std_logic_vector(Data-1 downto 0);
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signal RC_RSV, RC_EPC, RC_TID, RC_USR : std_logic;
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signal RC_RSV, RC_EPC, RC_TID, RC_USR : std_logic;
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-- Internal regs
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-- Internal regs
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signal DTI_r : std_logic_vector(Data-1 downto 0);
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signal DTI_r : std_logic_vector(Data-1 downto 0);
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signal DTO_r : std_logic_vector(Data-1 downto 0);
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signal DTO_r : std_logic_vector(Data-1 downto 0);
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signal ADR_r : std_logic_vector((2*AddrUSR)-1 downto 0);
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signal ADR_r : std_logic_vector((2*AddrUSR)-1 downto 0);
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signal BNK_r : std_logic_vector(1 downto 0);
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signal BNK_r : std_logic_vector(1 downto 0);
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signal ADR_ce, DTI_ce, DTO_ce, BNK_ce : std_logic;
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signal ADR_ce, DTI_ce, DTO_ce, BNK_ce : std_logic;
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-- Internal Flags & other signals
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-- Internal Flags & other signals
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signal AddrMux : std_logic;
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signal AddrMux : std_logic;
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signal WRCmdFlag, WRCmdFlag_i : std_logic;
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signal WRCmdFlag, WRCmdFlag_i : std_logic;
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|
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begin -- Mem_Ctrl_arch
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begin -- Mem_Ctrl_arch
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|
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|
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SYNC_MEMCTRL : process (clk, rst_n)
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SYNC_MEMCTRL : process (clk, rst_n)
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begin -- process SYNC
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begin -- process SYNC
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if rst_n = '0' then -- asynchronous reset (active low)
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if rst_n = '0' then -- asynchronous reset (active low)
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StMCtrl <= st_idle;
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StMCtrl <= st_idle;
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RC <= '1'; -- 1 -> 0 : Load LSB address
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RC <= '1'; -- 1 -> 0 : Load LSB address
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G <= '1'; -- 0: enable
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G <= '1'; -- 0: enable
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W <= '0';
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W <= '0';
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WRCmdFlag <= '0';
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WRCmdFlag <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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StMCtrl <= NextStMCtrl;
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StMCtrl <= NextStMCtrl;
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RC <= RC_i;
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RC <= RC_i;
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G <= G_i;
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G <= G_i;
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W <= W_i;
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W <= W_i;
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WRCmdFlag <= WRCmdFlag_i;
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WRCmdFlag <= WRCmdFlag_i;
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end if;
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end if;
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end process SYNC_MEMCTRL;
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end process SYNC_MEMCTRL;
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NEXTST_MEMCTRL : process (StMCtrl, WR, RD, ADR, DTI)
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NEXTST_MEMCTRL : process (StMCtrl, WR, RD, ADR, DTI)
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begin -- process NEXTST
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begin -- process NEXTST
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|
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NextStMCtrl <= StMCtrl;
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NextStMCtrl <= StMCtrl;
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|
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case StMCtrl is
|
case StMCtrl is
|
when st_idle =>
|
when st_idle =>
|
if WR = '1' then
|
if WR = '1' then
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NextStMCtrl <= st_write_LoadAddr1;
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NextStMCtrl <= st_write_LoadAddr1;
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elsif RD = '1' then
|
elsif RD = '1' then
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NextStMCtrl <= st_read_LoadAddr1;
|
NextStMCtrl <= st_read_LoadAddr1;
|
end if;
|
end if;
|
when st_read_LoadAddr1 =>
|
when st_read_LoadAddr1 =>
|
NextStMCtrl <= st_read_LoadAddr2;
|
NextStMCtrl <= st_read_LoadAddr2;
|
when st_read_LoadAddr2 =>
|
when st_read_LoadAddr2 =>
|
NextStMCtrl <= st_read_read;
|
NextStMCtrl <= st_read_read;
|
when st_read_read =>
|
when st_read_read =>
|
NextStMCtrl <= st_read_LoadOutput;
|
NextStMCtrl <= st_read_LoadOutput;
|
when st_read_LoadOutput =>
|
when st_read_LoadOutput =>
|
NextStMCtrl <= st_idle;
|
NextStMCtrl <= st_idle;
|
|
|
when st_write_LoadAddr1 =>
|
when st_write_LoadAddr1 =>
|
NextStMCtrl <= st_write_LoadAddr2;
|
NextStMCtrl <= st_write_LoadAddr2;
|
when st_write_LoadAddr2 =>
|
when st_write_LoadAddr2 =>
|
NextStMCtrl <= st_write_write;
|
NextStMCtrl <= st_write_write;
|
when st_write_write =>
|
when st_write_write =>
|
NextStMCtrl <= st_idle;
|
NextStMCtrl <= st_idle;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
end process NEXTST_MEMCTRL;
|
end process NEXTST_MEMCTRL;
|
|
|
|
|
OUTPUT_MEMCTRL : process (StMCtrl, WR, RD)
|
OUTPUT_MEMCTRL : process (StMCtrl, WR, RD)
|
begin -- process OUTPUT_MEMCTRL
|
begin -- process OUTPUT_MEMCTRL
|
|
|
RB <= '0';
|
RB <= '0';
|
ADR_ce <= '0';
|
ADR_ce <= '0';
|
DTI_ce <= '0';
|
DTI_ce <= '0';
|
DTO_ce <= '0';
|
DTO_ce <= '0';
|
BNK_ce <= '0';
|
BNK_ce <= '0';
|
AddrMux <= '0';
|
AddrMux <= '0';
|
WRCmdFlag_i <= '0';
|
WRCmdFlag_i <= '0';
|
-- Memory signals
|
-- Memory signals
|
RC_i <= '1';
|
RC_i <= '1';
|
G_i <= '1';
|
G_i <= '1';
|
W_i <= '0';
|
W_i <= '0';
|
|
|
case StMCtrl is
|
case StMCtrl is
|
when st_idle =>
|
when st_idle =>
|
RB <= '1';
|
RB <= '1';
|
if WR = '1' then
|
if WR = '1' then
|
ADR_ce <= '1'; -- load address
|
ADR_ce <= '1'; -- load address
|
DTI_ce <= '1'; -- load data
|
DTI_ce <= '1'; -- load data
|
BNK_ce <= '1'; -- load Bank
|
BNK_ce <= '1'; -- load Bank
|
RB <= '0';
|
RB <= '0';
|
elsif RD = '1' then
|
elsif RD = '1' then
|
ADR_ce <= '1'; -- load address
|
ADR_ce <= '1'; -- load address
|
BNK_ce <= '1'; -- load Bank
|
BNK_ce <= '1'; -- load Bank
|
RB <= '0';
|
RB <= '0';
|
end if;
|
end if;
|
|
|
when st_read_LoadAddr1 =>
|
when st_read_LoadAddr1 =>
|
RC_i <= '0'; -- Load Address LSB
|
RC_i <= '0'; -- Load Address LSB
|
|
|
when st_read_LoadAddr2 =>
|
when st_read_LoadAddr2 =>
|
AddrMux <= '1'; -- Load Address MSB
|
AddrMux <= '1'; -- Load Address MSB
|
|
|
when st_read_read =>
|
when st_read_read =>
|
G_i <= '0'; -- Read Command
|
G_i <= '0'; -- Read Command
|
|
|
when st_read_LoadOutput =>
|
when st_read_LoadOutput =>
|
DTO_ce <= '1'; -- Load output register
|
DTO_ce <= '1'; -- Load output register
|
|
|
when st_write_LoadAddr1 =>
|
when st_write_LoadAddr1 =>
|
RC_i <= '0'; -- Load Address LSB
|
RC_i <= '0'; -- Load Address LSB
|
WRCmdFlag_i <= '1'; -- Load Write Command code
|
WRCmdFlag_i <= '1'; -- Load Write Command code
|
W_i <= '1';
|
W_i <= '1';
|
|
|
when st_write_LoadAddr2 =>
|
when st_write_LoadAddr2 =>
|
AddrMux <= '1'; -- Load Address MSB
|
AddrMux <= '1'; -- Load Address MSB
|
|
|
when st_write_write =>
|
when st_write_write =>
|
W_i <= '1'; -- Write Data
|
W_i <= '1'; -- Write Data
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end process OUTPUT_MEMCTRL;
|
end process OUTPUT_MEMCTRL;
|
|
|
|
|
|
|
INTREGS : process (clk, rst_n)
|
INTREGS : process (clk, rst_n)
|
begin -- process INTREGS
|
begin -- process INTREGS
|
if rst_n = '0' then -- asynchronous reset (active low)
|
if rst_n = '0' then -- asynchronous reset (active low)
|
ADR_r <= (others => '0');
|
ADR_r <= (others => '0');
|
DTI_r <= (others => '0');
|
DTI_r <= (others => '0');
|
DTO_r <= (others => '0');
|
DTO_r <= (others => '0');
|
BNK_r <= (others => '0');
|
BNK_r <= (others => '0');
|
elsif clk'event and clk = '1' then -- rising clock edge
|
elsif clk'event and clk = '1' then -- rising clock edge
|
if ADR_ce = '1' then
|
if ADR_ce = '1' then
|
ADR_r <= ADR;
|
ADR_r <= ADR;
|
end if;
|
end if;
|
if DTI_ce = '1' then
|
if DTI_ce = '1' then
|
DTI_r <= DTI;
|
DTI_r <= DTI;
|
end if;
|
end if;
|
if DTO_ce = '1' then
|
if DTO_ce = '1' then
|
DTO_r <= Q;
|
DTO_r <= Q;
|
end if;
|
end if;
|
if BNK_ce = '1' then
|
if BNK_ce = '1' then
|
BNK_r <= BANK;
|
BNK_r <= BANK;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process INTREGS;
|
end process INTREGS;
|
|
|
|
|
DTO <= DTO_r;
|
DTO <= DTO_r;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- ADDRESS MUX
|
-- ADDRESS MUX
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
A_RSV <= ADR_r(AddrRSV-1 downto 0) when AddrMux = '0' else
|
A_RSV <= ADR_r(AddrRSV-1 downto 0) when AddrMux = '0' else
|
ADR_r((2*AddrRSV)-1 downto AddrRSV);
|
ADR_r((2*AddrRSV)-1 downto AddrRSV);
|
|
|
A_EPC <= ADR_r(AddrEPC-1 downto 0) when AddrMux = '0' else
|
A_EPC <= ADR_r(AddrEPC-1 downto 0) when AddrMux = '0' else
|
ADR_r((2*AddrEPC)-1 downto AddrEPC);
|
ADR_r((2*AddrEPC)-1 downto AddrEPC);
|
|
|
A_TID <= ADR_r(AddrTID-1 downto 0) when AddrMux = '0' else
|
A_TID <= ADR_r(AddrTID-1 downto 0) when AddrMux = '0' else
|
ADR_r((2*AddrTID)-1 downto AddrTID);
|
ADR_r((2*AddrTID)-1 downto AddrTID);
|
|
|
A_USR <= ADR_r(AddrUSR-1 downto 0) when AddrMux = '0' else
|
A_USR <= ADR_r(AddrUSR-1 downto 0) when AddrMux = '0' else
|
ADR_r((2*AddrUSR)-1 downto AddrUSR);
|
ADR_r((2*AddrUSR)-1 downto AddrUSR);
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- DATA IN MUX
|
-- DATA IN MUX
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
D <= WriteCommand when WRCmdFlag = '1' else
|
D <= WriteCommand when WRCmdFlag = '1' else
|
DTI_r;
|
DTI_r;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- CONTROL SIGNALS MUXs
|
-- CONTROL SIGNALS MUXs
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
W_RSV <= W when BNK_r = "00" else
|
W_RSV <= W when BNK_r = "00" else
|
'0';
|
'0';
|
W_EPC <= W when BNK_r = "01" else
|
W_EPC <= W when BNK_r = "01" else
|
'0';
|
'0';
|
W_TID <= W when BNK_r = "10" else
|
W_TID <= W when BNK_r = "10" else
|
'0';
|
'0';
|
W_USR <= W when BNK_r = "11" else
|
W_USR <= W when BNK_r = "11" else
|
'0';
|
'0';
|
|
|
|
|
G_RSV <= G when BNK_r = "00" else
|
G_RSV <= G when BNK_r = "00" else
|
'1';
|
'1';
|
G_EPC <= G when BNK_r = "01" else
|
G_EPC <= G when BNK_r = "01" else
|
'1';
|
'1';
|
G_TID <= G when BNK_r = "10" else
|
G_TID <= G when BNK_r = "10" else
|
'1';
|
'1';
|
G_USR <= G when BNK_r = "11" else
|
G_USR <= G when BNK_r = "11" else
|
'1';
|
'1';
|
|
|
RC_RSV <= RC when BNK_r = "00" else
|
RC_RSV <= RC when BNK_r = "00" else
|
'1';
|
'1';
|
RC_EPC <= RC when BNK_r = "01" else
|
RC_EPC <= RC when BNK_r = "01" else
|
'1';
|
'1';
|
RC_TID <= RC when BNK_r = "10" else
|
RC_TID <= RC when BNK_r = "10" else
|
'1';
|
'1';
|
RC_USR <= RC when BNK_r = "11" else
|
RC_USR <= RC when BNK_r = "11" else
|
'1';
|
'1';
|
|
|
Q <= Q_RSV when BNK_r = "00" else
|
Q <= Q_RSV when BNK_r = "00" else
|
Q_EPC when BNK_r = "01" else
|
Q_EPC when BNK_r = "01" else
|
Q_TID when BNK_r = "10" else
|
Q_TID when BNK_r = "10" else
|
Q_USR;
|
Q_USR;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- MEMORIES
|
-- MEMORIES
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Flash_MeM_RSV_i : Flash_MeM_RSV
|
Flash_MeM_RSV_i : Flash_MeM_RSV
|
generic map (
|
generic map (
|
Words => WordsRSV,
|
Words => WordsRSV,
|
Addr => AddrRSV,
|
Addr => AddrRSV,
|
Data => Data)
|
Data => Data)
|
port map (
|
port map (
|
A => A_RSV,
|
A => A_RSV,
|
D => D,
|
D => D,
|
Q => Q_RSV,
|
Q => Q_RSV,
|
G => G_RSV,
|
G => G_RSV,
|
W => W_RSV,
|
W => W_RSV,
|
RC => RC_RSV,
|
RC => RC_RSV,
|
st => st);
|
st => st);
|
|
|
Flash_MeM_EPC_i : Flash_MeM_EPC
|
Flash_MeM_EPC_i : Flash_MeM_EPC
|
generic map (
|
generic map (
|
Words => WordsEPC,
|
Words => WordsEPC,
|
Addr => AddrEPC,
|
Addr => AddrEPC,
|
Data => Data)
|
Data => Data)
|
port map (
|
port map (
|
A => A_EPC,
|
A => A_EPC,
|
D => D,
|
D => D,
|
Q => Q_EPC,
|
Q => Q_EPC,
|
G => G_EPC,
|
G => G_EPC,
|
W => W_EPC,
|
W => W_EPC,
|
RC => RC_EPC,
|
RC => RC_EPC,
|
st => st);
|
st => st);
|
|
|
Flash_MeM_TID_i : Flash_MeM_TID
|
Flash_MeM_TID_i : Flash_MeM_TID
|
generic map (
|
generic map (
|
Words => WordsTID,
|
Words => WordsTID,
|
Addr => AddrTID,
|
Addr => AddrTID,
|
Data => Data)
|
Data => Data)
|
port map (
|
port map (
|
A => A_TID,
|
A => A_TID,
|
D => D,
|
D => D,
|
Q => Q_TID,
|
Q => Q_TID,
|
G => G_TID,
|
G => G_TID,
|
W => W_TID,
|
W => W_TID,
|
RC => RC_TID,
|
RC => RC_TID,
|
st => st);
|
st => st);
|
|
|
Flash_MeM_USR_i : Flash_MeM_USR
|
Flash_MeM_USR_i : Flash_MeM_USR
|
generic map (
|
generic map (
|
Words => WordsUSR,
|
Words => WordsUSR,
|
Addr => AddrUSR,
|
Addr => AddrUSR,
|
Data => Data)
|
Data => Data)
|
port map (
|
port map (
|
A => A_USR,
|
A => A_USR,
|
D => D,
|
D => D,
|
Q => Q_USR,
|
Q => Q_USR,
|
G => G_USR,
|
G => G_USR,
|
W => W_USR,
|
W => W_USR,
|
RC => RC_USR,
|
RC => RC_USR,
|
st => st);
|
st => st);
|
|
|
end Mem_Ctrl_arch;
|
end Mem_Ctrl_arch;
|
|
|