-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Politecnico di Torino
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-- Politecnico di Torino
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-- Dipartimento di Automatica e Informatica
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-- Dipartimento di Automatica e Informatica
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : Shift Register
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-- Title : Shift Register
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--
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--
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-- File name : shiftreg.vhd
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-- File name : shiftreg.vhd
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--
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--
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-- Description : Simple Shift Register
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-- Description : Simple Shift Register
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--
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--
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-- Authors : Erwing R. Sanchez <erwing.sanchezsanchez@polito.it>
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-- Authors : Erwing R. Sanchez <erwing.sanchez@polito.it>
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--
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-- Rev. History : 30 June 06
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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entity shiftreg is
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entity shiftreg is
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generic (
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generic (
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REGWD : integer := 16);
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REGWD : integer := 16);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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ce : in std_logic;
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ce : in std_logic;
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sin : in std_logic;
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sin : in std_logic;
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pout : out std_logic_vector(REGWD - 1 downto 0));
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pout : out std_logic_vector(REGWD - 1 downto 0));
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end shiftreg;
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end shiftreg;
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architecture shreg1 of shiftreg is
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architecture shreg1 of shiftreg is
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signal shreg : std_logic_vector(REGWD-1 downto 0);
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signal shreg : std_logic_vector(REGWD-1 downto 0);
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begin -- shreg1
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begin -- shreg1
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process (clk , rst_n)
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process (clk , rst_n)
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begin
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begin
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if rst_n = '0' then
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if rst_n = '0' then
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shreg <= (others => '0');
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shreg <= (others => '0');
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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if ce = '1' then
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if ce = '1' then
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shreg <= shreg((REGWD - 2) downto 0) & sin;
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shreg <= shreg((REGWD - 2) downto 0) & sin;
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end if;
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end if;
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end if;
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end if;
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pout <= shreg;
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pout <= shreg;
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end process;
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end process;
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end shreg1;
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end shreg1;
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