OpenCores
URL https://opencores.org/ocsvn/esoc/esoc/trunk

Subversion Repositories esoc

[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [esoc_pll1_c3/] [syn.psm] - Diff between revs 41 and 54

Only display areas with differences | Details | Blame | View Log

Rev 41 Rev 54
4%@7
[+]
/Hu
4-@
    



;
88888ieee.std_logic_1164.std_logic_vectortorstd.standard.bit_vector8888888inclk0lLL-c0lLL.c1lLL/(c2lLL0HlockedkLL1hsub_wire0reLL8sub_wire1reLL9sub_wire2reLL:sub_wire3reLL;sub_wire4reLL<(sub_wire5reLL=Psub_wire6reLL>xsub_wire7_bv_bvLL?sub_wire7reLL@line__14214line__14314line__14414line__14514line__14614line__14714line__14814line__14914line__15015line__15115line__15215altpll_componententAUTO`obandwidth_typeyclk0_divide_by_clk0_duty_cycleclk0_multiply_by_by0clk0_phase_shiftiftclk1_divide_by_clk1_duty_cycleclk1_multiply_by_by0      clk1_phase_shiftiftclk2_divide_by_clk2_duty_cycleclk2_multiply_by_by0Yclk2_phase_shiftiftCLK0`ycompensate_clockockinclk0_input_frequencynCyclone IIIintended_device_familyiCBX_MODULE_PREFIX=esoc_pll1_c3lpm_hintintaltpll@lpm_typeypeNORMAL@)operation_modeoAUTO`Gpll_typeypePORT_UNUSEDaport_activeclockockPORT_UNUSEDport_aresetPORT_UNUSEDport_clkbad0ad0PORT_UNUSEDport_clkbad1ad1PORT_UNUSEDport_clklossossPORT_UNUSED
port_clkswitchtPORT_UNUSED/port_configupdateatPORT_UNUSEDZport_fbinbiPORT_USEDxzport_inclk0PORT_UNUSEDport_inclk1PORT_USEDxport_lockedPORT_UNUSEDport_pfdenaPORT_UNUSEDport_phasecounterselectPORT_UNUSED(        port_phasedoneoPORT_UNUSEDO port_phasesteptPORT_UNUSEDw port_phaseupdownownPORT_UNUSED port_pllenaPORT_UNUSED port_scanaclrclPORT_UNUSED port_scanclkclkPORT_UNUSED


port_scanclkenaPORT_UNUSED0
8


port_scandataatPORT_UNUSEDV


port_scandataoutoutPORT_UNUSED
h


port_scandoneonPORT_UNUSED


port_scanreadeaPORT_UNUSED



port_scanwriteiPORT_USEDx


port_clk0lkPORT_USEDxport_clk1lkPORT_USEDx2port_clk2lkPORT_UNUSEDRport_clk3lkPORT_UNUSEDrport_clk4lkPORT_UNUSEDport_clk5lkPORT_UNUSEDport_clkena0na0PORT_UNUSEDport_clkena1na1PORT_UNUSEDport_clkena2na2PORT_UNUSEDport_clkena3na3PORT_UNUSED5port_clkena4na4PORT_UNUSEDUport_clkena5na5PORT_UNUSEDuport_extclk0lk0PORT_UNUSEDport_extclk1lk1PORT_UNUSEDport_extclk2lk2PORT_UNUSEDport_extclk3lk3ONself_reset_on_loss_lockwidth_clockinclkclclk^altpllpaltera_mf_mK
workorkieeeeee\
a
K
xt
synesoc_pll1_c3_c3c:/data/temp/ESoC/Sources/altera/esoc_pll1_c3/esoc_pll1_c3.vhdv




W  /u
8
        


h
        



        

 

        

@

        

 
(        
 

x
X
        

E


$
 
-n-

d

/
`        
.n-

d
        
/
        
/n-

d
        
/
@        
0n-

d
x         
 /
        
1n$-$

d

(/
$
!
-u-
8n0

0
d
/
8/
/.u-
9n<-0<

d

@/
 /
:nD-PD

d
//u$-0$
H/

;nL-     pL

d
0/
P/
,/$0u4-P4
<nT-

T

d
@/
X/
</41uD-pD

=n\-\

d
P/
`/
L/D!
>nh8
8uX
h8
d
X
p/

?nxh
d/

xh
d
9uh-h
/

@n
p/

d
:ut-     t
/

 t
|/
6
;u-     


x.

*t
/
6
<u-

8
.

/
he
4t
=u-`
6

P
/

P
>u@
 8

@
0


/

8e
?ux
        >t

x
6

H
/

H
@u
 8

0


/

8e


Ht
6
6

@


@
6
 8

0


6

8e

Rt

6
6





@
6

@e
"
\t

6
6

,



H
6

He
6

ft

6
6
 
@

 

P
6

Pe
J
pt

6
6
(
T

(

X
6

Xe

zt
/^
6
X

`
,c
buu`

`
x

u

e
u2
t
u
6
u
p

h.
u
u2
e
u
`
u

`e


u)
S
u82
^]n8
uH


uh
n


`
n

2
u`
n



nh
u N


u
n        



n

2
u
n(



nHh
u @

@

nY


u8@
nh

2
0
nx


uX`
nh
P


ux
n8
p


u
n

 N

n
u



n8
u

0

nP
u

H

nh
u 

`

n8
uH


@
n
up


h
n
ux



n
u



n
ux



n0
u

(

nP
u       

H
        
nx
u@       

p
8        
n
uh       


`        
n(
u       


        
n
u       


        
n(
u       


        
n 
u



n@
        

8
u
np


h

n



uH
n



@
n



up
n       


        
h
n0       


(        
u
nP       


H        

nx       


p        
u
n       


        

n       


        
u
n       


        

n


ux




u(x
n8
 
(
uHx

0
@

uh
nX
`
(
u

P


u
nx

(
u

p


u
n


u




u(
n
 

uH


@

uh
n
`

u




u
n


u




u
n



u

n8


0
u

nX
$
@@       

P
h       
nx
*
       

p
0
D
X
\
h

n
/


c     b
n
W


4^
n
X


c
n
b


W8-ud
n
/


*/
n0X
.u d

(
/
nH


*/
nT88
p
/u$0d
p
(/
n


X
*(,/
X
0u4@d
n 8
8/
0Z
8
*8</
`x
1uDPd
]]]m        
H/
-
*HL/
]]mx
!
8uXdd
-
`/
q
9uhpd
]]m0
l/
:ut|d

x/

;ud
]        ]m0
/
<u d

/

=u!d
]
/!
]m0
>u"d
/"

?u#d

/#
]]m
@u$d
<
/$
]]m
%^
D
%X%
!]
]m
Dcbu    
L
u&;$
&
#]]m
    
T
u';h'
%]]m
    
#
u(;d*
(

    

       

8cb
']]m\
}
W8

-
u.
q

)]]


u.
*]+]00000ieee.std_logic_1164.std_logic_vectortorstd.standard.bit_vector0000000inclk0lLL-c0lLL.c1lLL/c2lLL0lockedkLL1sub_wire0reLL8sub_wire1reLL9 sub_wire2reLL:@sub_wire3reLL;`sub_wire4reLL<sub_wire5reLL=sub_wire6reLL>sub_wire7_bv_bvLL?sub_wire7reLL@line__14214line__14314line__14414line__14514line__14614line__14714line__14814line__14914line__15015line__15115line__15215altpll_componententAUTO8bandwidth_typeyclk0_divide_by_clk0_duty_cycleclk0_multiply_by_by0hclk0_phase_shiftiftclk1_divide_by_clk1_duty_cycleclk1_multiply_by_by0h9clk1_phase_shiftiftclk2_divide_by_clk2_duty_cycleclk2_multiply_by_by0hclk2_phase_shiftiftCLK08compensate_clockockinclk0_input_frequencynCyclone IIIintended_device_familyiCBX_MODULE_PREFIX=esoc_pll1_c3lpm_hintintaltpllAlpm_typeypeNORMALYoperation_modeoAUTO8wpll_typeypePORT_UNUSEDport_activeclockockPORT_UNUSEDport_aresetPORT_UNUSEDport_clkbad0ad0PORT_UNUSEDport_clkbad1ad1PORT_UNUSEDport_clklossossPORT_UNUSED=port_clkswitchtPORT_UNUSED_port_configupdateatPORT_UNUSEDport_fbinbiPORT_USED(port_inclk0PORT_UNUSEDport_inclk1PORT_USED(port_lockedPORT_UNUSEDport_pfdenaPORT_UNUSED,port_phasecounterselectPORT_UNUSEDXport_phasedoneoPORT_UNUSEDport_phasesteptPORT_UNUSEDport_phaseupdownownPORT_UNUSEDport_pllenaPORT_UNUSEDport_scanaclrclPORT_UNUSED     port_scanclkclkPORT_UNUSED= port_scanclkenaPORT_UNUSED` port_scandataatPORT_UNUSED port_scandataoutoutPORT_UNUSED port_scandoneonPORT_UNUSED port_scanreadeaPORT_UNUSED port_scanwriteiPORT_USED('
xe
port_clk0lkPORT_USED(B

port_clk1lkPORT_USED(b

port_clk2lkPORT_UNUSED
u
port_clk3lkPORT_UNUSED
)+`0*)
port_clk4lkPORT_UNUSED
++`0,+
port_clk5lkPORT_UNUSED
*
 
,
 
e
 

 

 
uxx
 
-+`0.-
 
/+`00/
 
.
 
0
 
e
 

 

 
ull
 
1+`021
 
3+`043
 
2
 
4
 
e
 

 

 
u
 
lle
 

 

 
u((
 
xxe
 

 

 
u88
 
e
 

 

 
uHH
 
e
 

 

 
u
 
e
 

 

 
u.
 
e
 
e
 

 
/(
 

 
b;

 
;
 
bt     x
-
 
t5
 
5-
 
q
 
t6X
 
6
 

 
t7X
 
7
 

 
t8X
 
8
 

 
th  
 
tt  
 
t  
 
t  
 
t99
 

 
t:  }
 
:-
 
q
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.