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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [esoc_port_mal_control/] [esoc_port_mal_control.psm] - Diff between revs 41 and 54

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Rev 41 Rev 54 
4%@D4CG]1
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.    88888ieee.std_logic_1164.std_logic_vectortoresoc_port_nr_nr`` eclk_controlLL"ctrl_addressessLL#ctrl_rdLL$ctrl_rddataLL%ctrl_waitaiLL& ctrl_wrLL'Hctrl_wrdataLL(hforce_vlan_default_in_iLL)force_vlan_default_outoLL*magic_sleep_np_LL+magic_wakeupeupLL,port_vlan_defaultulLL-@resetseLL.pxoff_gengenLL/xon_genLL0reg_port_mal_vlan_defaultulLLBreg_port_mal_stat_ctrltLLH8hctrl_rddata_ia_LLRctrl_wait_iLLSctrl_bus_enableLLTregisterserline__14914line__15015line__15315line__15415line__15615line__15815line__15915line__16016esoc_port_mal_controlroreg_port_mal_vlan_default_addadreg_port_mal_vlan_default_rstrsreg_port_mal_vlan_default_force_outreg_port_mal_vlan_default_force_in_reg_port_mal_stat_ctrl_addareg_port_mal_stat_ctrl_rstrreg_port_mal_stat_ctrl_xon_gengreg_port_mal_stat_ctrl_xoff_genreg_port_mal_stat_ctrl_magic_wakeupreg_port_mal_stat_ctrl_magic_sleepec:/data/temp/ESoC/Sources/logixa/esoc_port_mal_control.vhdv9
 


 
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