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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [esoc_port_storage/] [structure.prw] - Diff between revs 41 and 54

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Rev 41 Rev 54
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4-`
8888888888888ieee.std_logic_1164.std_logic_vectortorclk_controlLL8clk_dataataLL90clk_searchrLL:Xinbound_port_dataatLL;inbound_port_data_fulluLL<inbound_port_data_writeLL=inbound_port_headerLL>inbound_port_header_writeitLL?@inbound_port_infonfLL@xinbound_port_info_writeLLAinbound_proc_dataatLLBinbound_proc_data_fulluLLCinbound_proc_data_readeLLD8inbound_proc_headerLLEhinbound_proc_header_emptyptLLFinbound_proc_header_readeadLLGinbound_proc_infonfLLHinbound_proc_info_emptyLLI8inbound_proc_info_readeLLJhoutbound_port_dataaLLKoutbound_port_data_readLLLoutbound_port_infonLLMoutbound_port_info_emptyptyLLN(outbound_port_info_readLLO`outbound_proc_dataaLLPoutbound_proc_data_fullLLQoutbound_proc_data_writeiteLLRoutbound_proc_infonLLS(outbound_proc_info_writeiteLLTXresetseLLUinbound_wrusedwLL_inbound_rdusedwLL`u1aclrclrdataatardclkclrdreqrewrclkclwrreqreqrerdemptyrdusedwwrfulluwrusedw  esoc_fifo_256x32x32workorkieeeeeestdm r w u4 esoc_fifo_256x11211m r w u51 esoc_fifo_256x16x16m r w u66 esoc_fifo_2kx32x64xm r w u0x0
8888888888888ieee.std_logic_1164.std_logic_vectortorclk_controlLL clk_dataataLL!0clk_searchrLL"Xinbound_port_dataatLL#inbound_port_data_fulluLL$inbound_port_data_writeLL%inbound_port_headerLL&inbound_port_header_writeitLL'@inbound_port_infonfLL(xinbound_port_info_writeLL)inbound_proc_dataatLL*inbound_proc_data_fulluLL+inbound_proc_data_readeLL,8inbound_proc_headerLL-hinbound_proc_header_emptyptLL.inbound_proc_header_readeadLL/inbound_proc_infonfLL0inbound_proc_info_emptyLL18inbound_proc_info_readeLL2houtbound_port_dataaLL3outbound_port_data_readLL4outbound_port_infonLL5outbound_port_info_emptyptyLL6(outbound_port_info_readLL7`outbound_proc_dataaLL8outbound_proc_data_fullLL9outbound_proc_data_writeiteLL:outbound_proc_infonLL;(outbound_proc_info_writeiteLL<XresetseLL=inbound_wrusedwLLGinbound_rdusedwLLHu1aclrclrdataatardclkclrdreqrewrclkclwrreqreqrerdemptyrdusedwwrfulluwrusedw esoc_fifo_256x32x32workorkieeeeeestdm r w u4 esoc_fifo_256x11211m r w u51 esoc_fifo_256x16x16m r w u66 esoc_fifo_2kx32x64xm r w u0x0
esoc_fifo_2kx64x32xm r w line__26226line__26526structureuresoc_port_storageagc:/data/temp/ESoC/Sources/logixa/esoc_port_storage.vhdv
esoc_fifo_2kx64x32xm r w line__23823line__24124structureuresoc_port_storageagc:/data/temp/ESoC/Sources/logixa/esoc_port_storage.vhdv
 
 

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