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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [esoc_ram_4kx1/] [syn.psm] - Diff between revs 41 and 54

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Rev 41 Rev 54
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{+7L8888ieee.std_logic_1164.std_logic_vectortor888888888address_as_LL-address_bs_LL.0clock_aLL/Xclock_bLL0xdata_aaLL1data_baLL2rden_anLL3rden_bnLL4wren_anLL5wren_bnLL68q_aLL7Xq_bLL8xsub_wire0reLL?sub_wire1reLL@line__11411line__11511altsyncram_componententCLOCK1address_reg_bg_BYPASS.clock_enable_input_at_aBYPASSUclock_enable_input_bt_bBYPASS}clock_enable_output_at_BYPASSclock_enable_output_bt_CLOCK1indata_reg_bg_besoc_ram_4kx1.mifHinit_fileilCyclone IIIintended_device_familyialtsyncram?lpm_typeypenumwords_asnumwords_bsBIDIR_DUAL_PORTwoperation_modeoNONE(outdata_aclr_arNONE(outdata_aclr_brUNREGISTERED`outdata_reg_ag_UNREGISTERED`outdata_reg_bg_FALSE.power_up_uninitializedzNEW_DATA_NO_NBE_READWread_during_write_mode_port_at_NEW_DATA_NO_NBE_READread_during_write_mode_port_bt_widthad_ad_widthad_bd_width_awidth_bwidth_byteena_awidth_byteena_bCLOCK1wrcontrol_wraddress_reg_bg_clock0cclock1caltsyncramraltera_mf_moworkorkieeeeeeosynesoc_ram_4kx1kxc:/data/temp/ESoC/Sources/altera/esoc_ram_nkx1/esoc_ram_4kx1.vhdvhd


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