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[/] [esoc/] [trunk/] [Simulation/] [Modelsim/] [work/] [esoc_ram_8kx80/] [syn.psm] - Diff between revs 41 and 54

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Rev 41 Rev 54
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R8888ieee.std_logic_1164.std_logic_vectortor88888888address_as_LL-address_bs_LL.clockocLL/ data_aaLL0@data_baLL1`rden_anLL2rden_bnLL3wren_anLL4wren_bnLL5q_aLL6q_bLL7 sub_wire0reLL>@sub_wire1reLL?hline__11211line__11311altsyncram_componententCLOCK0address_reg_bg_BYPASSclock_enable_input_at_aBYPASSclock_enable_input_bt_bBYPASS%clock_enable_output_at_BYPASSNclock_enable_output_bt_CLOCK0vindata_reg_bg_bCyclone IIIHintended_device_familyialtsyncramlpm_typeypenumwords_asnumwords_bsBIDIR_DUAL_PORToperation_modeoNONEoutdata_aclr_arNONE?outdata_aclr_brUNREGISTERED(_outdata_reg_ag_UNREGISTERED(outdata_reg_bg_FALSE`power_up_uninitializedzOLD_DATAread_during_write_mode_mixed_portsrOLD_DATAread_during_write_mode_port_at_OLD_DATA>read_during_write_mode_port_bt_widthad_ad_widthad_bd_width_awidth_bwidth_byteena_awidth_byteena_bCLOCK0wrcontrol_wraddress_reg_bg_clock0caltsyncramraltera_mf_mworkorkieeeeeesynesoc_ram_8kx80xc:/data/temp/ESoC/Sources/altera/esoc_ram_nkx80/esoc_ram_8kx80.vhdv?


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