--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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--
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---- Ethernet Switch on Configurable Logic IP Core ----
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
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---- ----
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--
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---- This file is part of the ESoCL project ----
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-- Ease library : work
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---- http://www.opencores.org/cores/esoc/ ----
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-- HDL library : work
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---- ----
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-- Host name : S212065
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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-- User name : df768
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---- ----
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-- Time stamp : Tue Aug 19 08:05:18 2014
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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--
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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-- Designed by : L.Maarsen
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---- ----
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-- Company : LogiXA
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---- Author(s): L.Maarsen ----
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-- Project info : eSoC
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---- Bert Maarsen, lmaarsen@opencores.org ----
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--
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.esoc_port_mal_control
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-- Object : Entity work.esoc_port_mal_control
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-- Last modified : Mon Apr 14 12:49:06 2014.
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-- Last modified : Mon Apr 14 12:49:06 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee, std, work;
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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use work.package_esoc_configuration.all;
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entity esoc_port_mal_control is
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entity esoc_port_mal_control is
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generic(
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generic(
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esoc_port_nr : integer := 0);
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esoc_port_nr : integer := 0);
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port(
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port(
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clk_control : in STD_LOGIC;
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clk_control : in STD_LOGIC;
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ctrl_address : in std_logic_vector(15 downto 0);
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ctrl_address : in std_logic_vector(15 downto 0);
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ctrl_rd : in std_logic := '0';
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ctrl_rd : in std_logic := '0';
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ctrl_rddata : out std_logic_vector(31 downto 0);
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ctrl_rddata : out std_logic_vector(31 downto 0);
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ctrl_wait : out STD_LOGIC;
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ctrl_wait : out STD_LOGIC;
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ctrl_wr : in std_logic;
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ctrl_wr : in std_logic;
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ctrl_wrdata : in std_logic_vector(31 downto 0);
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ctrl_wrdata : in std_logic_vector(31 downto 0);
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force_vlan_default_in : out std_logic;
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force_vlan_default_in : out std_logic;
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force_vlan_default_out : out std_logic;
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force_vlan_default_out : out std_logic;
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magic_sleep_n : out STD_LOGIC := '1';
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magic_sleep_n : out STD_LOGIC := '1';
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magic_wakeup : in STD_LOGIC;
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magic_wakeup : in STD_LOGIC;
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port_vlan_default : out std_logic_vector(15 downto 0);
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port_vlan_default : out std_logic_vector(15 downto 0);
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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xoff_gen : out STD_LOGIC;
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xoff_gen : out STD_LOGIC;
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xon_gen : out STD_LOGIC);
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xon_gen : out STD_LOGIC);
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end entity esoc_port_mal_control;
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end entity esoc_port_mal_control;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_port_mal_control.esoc_port_mal_control
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-- Object : Architecture work.esoc_port_mal_control.esoc_port_mal_control
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-- Last modified : Mon Apr 14 12:49:06 2014.
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-- Last modified : Mon Apr 14 12:49:06 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- architecture and declarations
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-- architecture and declarations
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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architecture esoc_port_mal_control of esoc_port_mal_control is
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architecture esoc_port_mal_control of esoc_port_mal_control is
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- registers
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-- registers
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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constant reg_port_mal_vlan_default_add: integer := 385;
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constant reg_port_mal_vlan_default_add: integer := 385;
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signal reg_port_mal_vlan_default: std_logic_vector(31 downto 0);
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signal reg_port_mal_vlan_default: std_logic_vector(31 downto 0);
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constant reg_port_mal_vlan_default_rst: std_logic_vector(31 downto 0) := X"00000001";
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constant reg_port_mal_vlan_default_rst: std_logic_vector(31 downto 0) := X"00000001";
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alias reg_port_mal_vlan_default_force_out: std_logic is reg_port_mal_vlan_default(31);
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alias reg_port_mal_vlan_default_force_out: std_logic is reg_port_mal_vlan_default(31);
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alias reg_port_mal_vlan_default_force_in : std_logic is reg_port_mal_vlan_default(30);
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alias reg_port_mal_vlan_default_force_in : std_logic is reg_port_mal_vlan_default(30);
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constant reg_port_mal_stat_ctrl_add : integer := 384;
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constant reg_port_mal_stat_ctrl_add : integer := 384;
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signal reg_port_mal_stat_ctrl : std_logic_vector(31 downto 0);
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signal reg_port_mal_stat_ctrl : std_logic_vector(31 downto 0);
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constant reg_port_mal_stat_ctrl_rst : std_logic_vector(31 downto 0) := X"00000001";
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constant reg_port_mal_stat_ctrl_rst : std_logic_vector(31 downto 0) := X"00000001";
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alias reg_port_mal_stat_ctrl_xon_gen : std_logic is reg_port_mal_stat_ctrl(3);
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alias reg_port_mal_stat_ctrl_xon_gen : std_logic is reg_port_mal_stat_ctrl(3);
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alias reg_port_mal_stat_ctrl_xoff_gen : std_logic is reg_port_mal_stat_ctrl(2);
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alias reg_port_mal_stat_ctrl_xoff_gen : std_logic is reg_port_mal_stat_ctrl(2);
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alias reg_port_mal_stat_ctrl_magic_wakeup: std_logic is reg_port_mal_stat_ctrl(1);
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alias reg_port_mal_stat_ctrl_magic_wakeup: std_logic is reg_port_mal_stat_ctrl(1);
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alias reg_port_mal_stat_ctrl_magic_sleep : std_logic is reg_port_mal_stat_ctrl(0);
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alias reg_port_mal_stat_ctrl_magic_sleep : std_logic is reg_port_mal_stat_ctrl(0);
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- signals
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-- signals
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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signal ctrl_rddata_i: std_logic_vector(ctrl_rddata'high downto 0);
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signal ctrl_rddata_i: std_logic_vector(ctrl_rddata'high downto 0);
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signal ctrl_wait_i: std_logic;
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signal ctrl_wait_i: std_logic;
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signal ctrl_bus_enable: std_logic;
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signal ctrl_bus_enable: std_logic;
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begin
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begin
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--=============================================================================================================
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--=============================================================================================================
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-- Process : access registers when addressed or provide data from other units to the ctrl_rddata_i bus
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-- Process : access registers when addressed or provide data from other units to the ctrl_rddata_i bus
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-- Description :
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-- Description :
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--=============================================================================================================
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--=============================================================================================================
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registers: process(clk_control, reset)
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registers: process(clk_control, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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reg_port_mal_vlan_default <= reg_port_mal_vlan_default_rst;
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reg_port_mal_vlan_default <= reg_port_mal_vlan_default_rst;
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-- all ports have weight 1 after reset
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-- all ports have weight 1 after reset
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reg_port_mal_stat_ctrl <= reg_port_mal_stat_ctrl_rst;
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reg_port_mal_stat_ctrl <= reg_port_mal_stat_ctrl_rst;
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ctrl_rddata_i <= (others => '0');
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ctrl_rddata_i <= (others => '0');
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ctrl_wait_i <= '1';
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ctrl_wait_i <= '1';
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ctrl_bus_enable <= '0';
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ctrl_bus_enable <= '0';
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elsif clk_control'event and clk_control = '1' then
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elsif clk_control'event and clk_control = '1' then
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reg_port_mal_stat_ctrl_magic_wakeup <= magic_wakeup;
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reg_port_mal_stat_ctrl_magic_wakeup <= magic_wakeup;
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ctrl_wait_i <= '1';
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ctrl_wait_i <= '1';
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ctrl_bus_enable <= '0';
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ctrl_bus_enable <= '0';
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-- continu if memory space of this entity is addressed
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-- continu if memory space of this entity is addressed
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if (to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mal_base) and (to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mal_base + esoc_port_mal_size) then
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if (to_integer(unsigned(ctrl_address)) >= esoc_port_nr * esoc_port_base_offset + esoc_port_mal_base) and (to_integer(unsigned(ctrl_address)) < esoc_port_nr * esoc_port_base_offset + esoc_port_mal_base + esoc_port_mal_size) then
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-- claim the bus for ctrl_wait and ctrl_rddata
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-- claim the bus for ctrl_wait and ctrl_rddata
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ctrl_bus_enable <= '1';
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ctrl_bus_enable <= '1';
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--
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--
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-- READ CYCLE started, unit addressed?
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-- READ CYCLE started, unit addressed?
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--
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--
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if ctrl_rd = '1' then
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if ctrl_rd = '1' then
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-- Check register address and provide data when addressed
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-- Check register address and provide data when addressed
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case to_integer(unsigned(ctrl_address))- esoc_port_nr * esoc_port_base_offset is
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case to_integer(unsigned(ctrl_address))- esoc_port_nr * esoc_port_base_offset is
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when reg_port_mal_vlan_default_add => ctrl_rddata_i <= reg_port_mal_vlan_default;
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when reg_port_mal_vlan_default_add => ctrl_rddata_i <= reg_port_mal_vlan_default;
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ctrl_wait_i <= '0';
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ctrl_wait_i <= '0';
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when reg_port_mal_stat_ctrl_add => ctrl_rddata_i <= reg_port_mal_stat_ctrl;
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when reg_port_mal_stat_ctrl_add => ctrl_rddata_i <= reg_port_mal_stat_ctrl;
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ctrl_wait_i <= '0';
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ctrl_wait_i <= '0';
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when others => NULL;
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when others => NULL;
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end case;
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end case;
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--
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--
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-- WRITE CYCLE started, unit addressed?
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-- WRITE CYCLE started, unit addressed?
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--
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--
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elsif ctrl_wr = '1' then
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elsif ctrl_wr = '1' then
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-- Check address and accept data when addressed
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-- Check address and accept data when addressed
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case to_integer(unsigned(ctrl_address))- esoc_port_nr * esoc_port_base_offset is
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case to_integer(unsigned(ctrl_address))- esoc_port_nr * esoc_port_base_offset is
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when reg_port_mal_vlan_default_add => reg_port_mal_vlan_default <= ctrl_wrdata;
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when reg_port_mal_vlan_default_add => reg_port_mal_vlan_default <= ctrl_wrdata;
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ctrl_wait_i <= '0';
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ctrl_wait_i <= '0';
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when reg_port_mal_stat_ctrl_add => reg_port_mal_stat_ctrl <= ctrl_wrdata;
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when reg_port_mal_stat_ctrl_add => reg_port_mal_stat_ctrl <= ctrl_wrdata;
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ctrl_wait_i <= '0';
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ctrl_wait_i <= '0';
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when others => NULL;
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when others => NULL;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Create tristate outputs
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-- Create tristate outputs
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ctrl_wait <= ctrl_wait_i when ctrl_bus_enable = '1' else 'Z';
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ctrl_wait <= ctrl_wait_i when ctrl_bus_enable = '1' else 'Z';
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ctrl_rddata <= ctrl_rddata_i when ctrl_bus_enable = '1' else (others => 'Z');
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ctrl_rddata <= ctrl_rddata_i when ctrl_bus_enable = '1' else (others => 'Z');
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-- use register content
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-- use register content
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force_vlan_default_out <= reg_port_mal_vlan_default_force_out;
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force_vlan_default_out <= reg_port_mal_vlan_default_force_out;
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force_vlan_default_in <= reg_port_mal_vlan_default_force_in;
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force_vlan_default_in <= reg_port_mal_vlan_default_force_in;
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port_vlan_default <= reg_port_mal_vlan_default(port_vlan_default'high downto 0);
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port_vlan_default <= reg_port_mal_vlan_default(port_vlan_default'high downto 0);
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magic_sleep_n <= reg_port_mal_stat_ctrl_magic_sleep;
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magic_sleep_n <= reg_port_mal_stat_ctrl_magic_sleep;
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xoff_gen <= reg_port_mal_stat_ctrl_xoff_gen;
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xoff_gen <= reg_port_mal_stat_ctrl_xoff_gen;
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xon_gen <= reg_port_mal_stat_ctrl_xon_gen;
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xon_gen <= reg_port_mal_stat_ctrl_xon_gen;
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end architecture esoc_port_mal_control ; -- of esoc_port_mal_control
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end architecture esoc_port_mal_control ; -- of esoc_port_mal_control
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