--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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--
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---- Ethernet Switch on Configurable Logic IP Core ----
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
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---- ----
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--
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---- This file is part of the ESoCL project ----
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-- Ease library : work
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---- http://www.opencores.org/cores/esoc/ ----
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-- HDL library : work
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---- ----
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-- Host name : S212065
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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-- User name : df768
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---- ----
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-- Time stamp : Tue Aug 19 08:05:18 2014
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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--
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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-- Designed by : L.Maarsen
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---- ----
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-- Company : LogiXA
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---- Author(s): L.Maarsen ----
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-- Project info : eSoC
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---- Bert Maarsen, lmaarsen@opencores.org ----
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--
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
|
|
---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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|
---- ----
|
|
---- You should have received a copy of the GNU Lesser General ----
|
|
---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.esoc_port_mal_inbound
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-- Object : Entity work.esoc_port_mal_inbound
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-- Last modified : Mon Apr 14 12:49:11 2014.
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-- Last modified : Mon Apr 14 12:49:11 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee, std, work;
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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use work.package_esoc_configuration.all;
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entity esoc_port_mal_inbound is
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entity esoc_port_mal_inbound is
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port(
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port(
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clk_control : in STD_LOGIC;
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clk_control : in STD_LOGIC;
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ff_rx_a_empty : in STD_LOGIC;
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ff_rx_a_empty : in STD_LOGIC;
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ff_rx_a_full : in STD_LOGIC;
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ff_rx_a_full : in STD_LOGIC;
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ff_rx_data : in STD_LOGIC_VECTOR(31 downto 0);
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ff_rx_data : in STD_LOGIC_VECTOR(31 downto 0);
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ff_rx_dsav : in STD_LOGIC;
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ff_rx_dsav : in STD_LOGIC;
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ff_rx_dval : in STD_LOGIC;
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ff_rx_dval : in STD_LOGIC;
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ff_rx_eop : in STD_LOGIC;
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ff_rx_eop : in STD_LOGIC;
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ff_rx_mod : in STD_LOGIC_VECTOR(1 downto 0);
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ff_rx_mod : in STD_LOGIC_VECTOR(1 downto 0);
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ff_rx_rdy : out STD_LOGIC;
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ff_rx_rdy : out STD_LOGIC;
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ff_rx_sop : in STD_LOGIC;
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ff_rx_sop : in STD_LOGIC;
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force_vlan_default_in : in std_logic;
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force_vlan_default_in : in std_logic;
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inbound_data : out std_logic_vector(31 downto 0);
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inbound_data : out std_logic_vector(31 downto 0);
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inbound_data_full : in std_logic;
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inbound_data_full : in std_logic;
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inbound_data_write : out std_logic;
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inbound_data_write : out std_logic;
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inbound_header : out std_logic_vector(111 downto 0);
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inbound_header : out std_logic_vector(111 downto 0);
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inbound_header_write : out std_logic;
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inbound_header_write : out std_logic;
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inbound_info : out std_logic_vector(31 downto 0);
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inbound_info : out std_logic_vector(31 downto 0);
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inbound_info_write : out std_logic;
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inbound_info_write : out std_logic;
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port_vlan_default : in std_logic_vector(15 downto 0);
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port_vlan_default : in std_logic_vector(15 downto 0);
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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rx_err_stat : in STD_LOGIC_VECTOR(17 downto 0);
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rx_err_stat : in STD_LOGIC_VECTOR(17 downto 0);
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rx_frm_type : in STD_LOGIC_VECTOR(3 downto 0));
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rx_frm_type : in STD_LOGIC_VECTOR(3 downto 0));
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end entity esoc_port_mal_inbound;
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end entity esoc_port_mal_inbound;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_port_mal_inbound.esoc_port_mal_inbound
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-- Object : Architecture work.esoc_port_mal_inbound.esoc_port_mal_inbound
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-- Last modified : Mon Apr 14 12:49:11 2014.
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-- Last modified : Mon Apr 14 12:49:11 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- architecture and declarations
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-- architecture and declarations
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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architecture esoc_port_mal_inbound of esoc_port_mal_inbound is
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architecture esoc_port_mal_inbound of esoc_port_mal_inbound is
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- registers
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-- registers
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- signals
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-- signals
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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signal ff_rx_counter: integer range 2**esoc_inbound_info_length_size-1 downto 0;
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signal ff_rx_counter: integer range 2**esoc_inbound_info_length_size-1 downto 0;
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signal boundary64: std_logic;
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signal boundary64: std_logic;
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signal boundary64_write: std_logic;
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signal boundary64_write: std_logic;
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begin
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begin
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--=============================================================================================================
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--=============================================================================================================
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-- Process : write header and information - DMAC, SMAC, VLAN ID, LENGTH, FLAGS - into HEADER and INFO FIFO
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-- Process : write header and information - DMAC, SMAC, VLAN ID, LENGTH, FLAGS - into HEADER and INFO FIFO
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-- Description : header information is used by the search process in the esoc_port_processor
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-- Description : header information is used by the search process in the esoc_port_processor
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-- info information is used by the data process in the esoc_port_processor
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-- info information is used by the data process in the esoc_port_processor
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--=============================================================================================================
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--=============================================================================================================
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infoheader: process(clk_control, reset)
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infoheader: process(clk_control, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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inbound_header <= (others => '0');
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inbound_header <= (others => '0');
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inbound_info <= (others => '0');
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inbound_info <= (others => '0');
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inbound_data <= (others => '0');
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inbound_data <= (others => '0');
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inbound_header_write <= '0';
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inbound_header_write <= '0';
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inbound_info_write <= '0';
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inbound_info_write <= '0';
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inbound_data_write <= '0';
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inbound_data_write <= '0';
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ff_rx_counter <= 0;
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ff_rx_counter <= 0;
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boundary64 <= '0';
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boundary64 <= '0';
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boundary64_write <= '0';
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boundary64_write <= '0';
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elsif clk_control'event and clk_control = '1' then
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elsif clk_control'event and clk_control = '1' then
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-- clear one-clock active signals
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-- clear one-clock active signals
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inbound_header_write <= '0';
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inbound_header_write <= '0';
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inbound_info_write <= '0';
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inbound_info_write <= '0';
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inbound_data_write <= '0';
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inbound_data_write <= '0';
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boundary64_write <= '0';
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boundary64_write <= '0';
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-- define unused bits to avoid inferred latch warning during analysis & synthesis
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-- define unused bits to avoid inferred latch warning during analysis & synthesis
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inbound_header(esoc_inbound_header_unused3_flag downto esoc_inbound_header_unused1_flag) <= (others => '0');
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inbound_header(esoc_inbound_header_unused3_flag downto esoc_inbound_header_unused1_flag) <= (others => '0');
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inbound_info(esoc_inbound_info_unused3_flag downto esoc_inbound_info_unused1_flag) <= (others => '0');
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inbound_info(esoc_inbound_info_unused3_flag downto esoc_inbound_info_unused1_flag) <= (others => '0');
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--
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--
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-- MONITOR THE ST INTERFACE TO MAC
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-- MONITOR THE ST INTERFACE TO MAC
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--
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--
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-- finalise packet storage, always write at 64b boundaries, because the other side of the FIFO has a width of 64 bit!
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-- finalise packet storage, always write at 64b boundaries, because the other side of the FIFO has a width of 64 bit!
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-- create dummy write if the packet at completion does not end on a 64 bit boundary.
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-- create dummy write if the packet at completion does not end on a 64 bit boundary.
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inbound_data_write <= boundary64_write;
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inbound_data_write <= boundary64_write;
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if ff_rx_dval = '1' then
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if ff_rx_dval = '1' then
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-- store data in FIFO
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-- store data in FIFO
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if ff_rx_sop = '1' or ff_rx_counter > 0 then
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if ff_rx_sop = '1' or ff_rx_counter > 0 then
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inbound_data_write <= '1';
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inbound_data_write <= '1';
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inbound_data <= ff_rx_data;
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inbound_data <= ff_rx_data;
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ff_rx_counter <= ff_rx_counter + 4;
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ff_rx_counter <= ff_rx_counter + 4;
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-- init boundary64 signal at start of new packet
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-- init boundary64 signal at start of new packet
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if ff_rx_sop = '1' then
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if ff_rx_sop = '1' then
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boundary64 <= '1';
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boundary64 <= '1';
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else
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else
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boundary64 <= not(boundary64);
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boundary64 <= not(boundary64);
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end if;
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end if;
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end if;
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end if;
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--
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--
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-- MANIPULATE DATA
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-- MANIPULATE DATA
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--
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--
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case ff_rx_counter is
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case ff_rx_counter is
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when 0 => -- store DMAC (4 MSbs) in data FIFO and prepare header FIFO input
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when 0 => -- store DMAC (4 MSbs) in data FIFO and prepare header FIFO input
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if ff_rx_sop = '1' then
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if ff_rx_sop = '1' then
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inbound_header(esoc_inbound_header_dmac_hi+31 downto esoc_inbound_header_dmac_hi) <= ff_rx_data;
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inbound_header(esoc_inbound_header_dmac_hi+31 downto esoc_inbound_header_dmac_hi) <= ff_rx_data;
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end if;
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end if;
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when 4 => -- store DMAC (2LSBs), SMAC (2MSBs) in data FIFO and prepare header FIFO input
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when 4 => -- store DMAC (2LSBs), SMAC (2MSBs) in data FIFO and prepare header FIFO input
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inbound_header(esoc_inbound_header_dmac_lo+15 downto esoc_inbound_header_smac_hi) <= ff_rx_data;
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inbound_header(esoc_inbound_header_dmac_lo+15 downto esoc_inbound_header_smac_hi) <= ff_rx_data;
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when 8 => -- store SMAC (4 LSBs) in data FIFO and prepare header FIFO input
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when 8 => -- store SMAC (4 LSBs) in data FIFO and prepare header FIFO input
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inbound_header(esoc_inbound_header_smac_lo+31 downto esoc_inbound_header_smac_lo) <= ff_rx_data;
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inbound_header(esoc_inbound_header_smac_lo+31 downto esoc_inbound_header_smac_lo) <= ff_rx_data;
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when 12 => -- tagged packet? store VLAN ID/TCI in data FIFO and prepare header FIFO input
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when 12 => -- tagged packet? store VLAN ID/TCI in data FIFO and prepare header FIFO input
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if ff_rx_data(31 downto 16) = esoc_ethernet_vlan_type then
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if ff_rx_data(31 downto 16) = esoc_ethernet_vlan_type then
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-- tagged with VLAN ID 0 is a QoS Packet only - or force default VLAN ID - replace VLAN ID with port default VLAN ID
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-- tagged with VLAN ID 0 is a QoS Packet only - or force default VLAN ID - replace VLAN ID with port default VLAN ID
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if ff_rx_data(11 downto 0) = esoc_ethernet_vlan_qos or force_vlan_default_in = '1' then
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if ff_rx_data(11 downto 0) = esoc_ethernet_vlan_qos or force_vlan_default_in = '1' then
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inbound_data(15 downto 0) <= port_vlan_default;
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inbound_data(15 downto 0) <= port_vlan_default;
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-- store default port VLAN ID in the header FIFO for the search operation
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-- store default port VLAN ID in the header FIFO for the search operation
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inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan) <= port_vlan_default(11 downto 0);
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inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan) <= port_vlan_default(11 downto 0);
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inbound_header(esoc_inbound_header_vlan_flag) <= '1';
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inbound_header(esoc_inbound_header_vlan_flag) <= '1';
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-- store default port VLAN tag in the info FIFO for the data transfer operation
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-- store default port VLAN tag in the info FIFO for the data transfer operation
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inbound_info(esoc_inbound_info_vlan_tci+15 downto esoc_inbound_info_vlan_tci) <= port_vlan_default;
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inbound_info(esoc_inbound_info_vlan_tci+15 downto esoc_inbound_info_vlan_tci) <= port_vlan_default;
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inbound_info(esoc_inbound_info_vlan_flag) <= '1';
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inbound_info(esoc_inbound_info_vlan_flag) <= '1';
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|
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-- tagged with VLAN ID > 0
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-- tagged with VLAN ID > 0
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else
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else
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-- store only VLAN ID in the header FIFO for the search operation
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-- store only VLAN ID in the header FIFO for the search operation
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inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan) <= ff_rx_data(11 downto 0);
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inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan) <= ff_rx_data(11 downto 0);
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inbound_header(esoc_inbound_header_vlan_flag) <= '1';
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inbound_header(esoc_inbound_header_vlan_flag) <= '1';
|
|
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-- store comlete VLAN tag in the info FIFO for the data transfer operation
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-- store comlete VLAN tag in the info FIFO for the data transfer operation
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inbound_info(esoc_inbound_info_vlan_tci+15 downto esoc_inbound_info_vlan_tci) <= ff_rx_data(15 downto 0);
|
inbound_info(esoc_inbound_info_vlan_tci+15 downto esoc_inbound_info_vlan_tci) <= ff_rx_data(15 downto 0);
|
inbound_info(esoc_inbound_info_vlan_flag) <= '1';
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inbound_info(esoc_inbound_info_vlan_flag) <= '1';
|
end if;
|
end if;
|
|
|
-- untagged packet
|
-- untagged packet
|
else
|
else
|
-- store default port VLAN ID in the header FIFO for the search operation
|
-- store default port VLAN ID in the header FIFO for the search operation
|
inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan) <= port_vlan_default(11 downto 0);
|
inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan) <= port_vlan_default(11 downto 0);
|
inbound_header(esoc_inbound_header_vlan_flag) <= '0';
|
inbound_header(esoc_inbound_header_vlan_flag) <= '0';
|
|
|
-- store default port VLAN tag in the info FIFO for the data transfer operation
|
-- store default port VLAN tag in the info FIFO for the data transfer operation
|
inbound_info(esoc_inbound_info_vlan_tci+15 downto esoc_inbound_info_vlan_tci) <= port_vlan_default;
|
inbound_info(esoc_inbound_info_vlan_tci+15 downto esoc_inbound_info_vlan_tci) <= port_vlan_default;
|
inbound_info(esoc_inbound_info_vlan_flag) <= '0';
|
inbound_info(esoc_inbound_info_vlan_flag) <= '0';
|
end if;
|
end if;
|
|
|
-- write header when complete, search operation can start!
|
-- write header when complete, search operation can start!
|
inbound_header_write <= '1';
|
inbound_header_write <= '1';
|
|
|
when others => -- Write information in to fifo when packet is complete, data operation can start!
|
when others => -- Write information in to fifo when packet is complete, data operation can start!
|
if ff_rx_eop = '1' then
|
if ff_rx_eop = '1' then
|
ff_rx_counter <= 0;
|
ff_rx_counter <= 0;
|
inbound_info(esoc_inbound_info_length+esoc_inbound_info_length_size-1 downto esoc_inbound_info_length) <= std_logic_vector(to_unsigned(ff_rx_counter + 4 - to_integer(unsigned(ff_rx_mod)),esoc_inbound_info_length_size));
|
inbound_info(esoc_inbound_info_length+esoc_inbound_info_length_size-1 downto esoc_inbound_info_length) <= std_logic_vector(to_unsigned(ff_rx_counter + 4 - to_integer(unsigned(ff_rx_mod)),esoc_inbound_info_length_size));
|
inbound_info_write <= '1';
|
inbound_info_write <= '1';
|
boundary64_write <= not(boundary64);
|
boundary64_write <= not(boundary64);
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--=============================================================================================================
|
--=============================================================================================================
|
-- Process : write packet into DATA FIFO
|
-- Process : write packet into DATA FIFO
|
-- Description :
|
-- Description :
|
--=============================================================================================================
|
--=============================================================================================================
|
-- FULL signal of FIFO is used to drive READY of ST Sink interface
|
-- FULL signal of FIFO is used to drive READY of ST Sink interface
|
ff_rx_rdy <= not(inbound_data_full);
|
ff_rx_rdy <= not(inbound_data_full);
|
|
|
end architecture esoc_port_mal_inbound ; -- of esoc_port_mal_inbound
|
end architecture esoc_port_mal_inbound ; -- of esoc_port_mal_inbound
|
|
|
