--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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--
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---- Ethernet Switch on Configurable Logic IP Core ----
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
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---- ----
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--
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---- This file is part of the ESoCL project ----
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-- Ease library : work
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---- http://www.opencores.org/cores/esoc/ ----
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-- HDL library : work
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---- ----
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-- Host name : S212065
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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-- User name : df768
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---- ----
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-- Time stamp : Tue Aug 19 08:05:18 2014
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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--
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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-- Designed by : L.Maarsen
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---- ----
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-- Company : LogiXA
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---- Author(s): L.Maarsen ----
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-- Project info : eSoC
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---- Bert Maarsen, lmaarsen@opencores.org ----
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--
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.esoc_port_mal_outbound
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-- Object : Entity work.esoc_port_mal_outbound
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-- Last modified : Mon Apr 14 12:49:17 2014.
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-- Last modified : Mon Apr 14 12:49:17 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee, std, work;
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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use work.package_esoc_configuration.all;
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entity esoc_port_mal_outbound is
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entity esoc_port_mal_outbound is
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port(
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port(
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clk_control : in STD_LOGIC;
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clk_control : in STD_LOGIC;
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ff_tx_a_empty : in STD_LOGIC;
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ff_tx_a_empty : in STD_LOGIC;
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ff_tx_a_full : in STD_LOGIC;
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ff_tx_a_full : in STD_LOGIC;
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ff_tx_crc_fwd : out STD_LOGIC;
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ff_tx_crc_fwd : out STD_LOGIC;
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ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);
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ff_tx_data : out STD_LOGIC_VECTOR(31 downto 0);
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ff_tx_eop : out STD_LOGIC;
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ff_tx_eop : out STD_LOGIC;
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ff_tx_err : out STD_LOGIC;
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ff_tx_err : out STD_LOGIC;
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ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);
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ff_tx_mod : out STD_LOGIC_VECTOR(1 downto 0);
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ff_tx_rdy : in STD_LOGIC;
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ff_tx_rdy : in STD_LOGIC;
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ff_tx_septy : in STD_LOGIC;
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ff_tx_septy : in STD_LOGIC;
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ff_tx_sop : out STD_LOGIC;
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ff_tx_sop : out STD_LOGIC;
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ff_tx_wren : out STD_LOGIC;
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ff_tx_wren : out STD_LOGIC;
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force_vlan_default_out : in std_logic;
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force_vlan_default_out : in std_logic;
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outbound_data : in std_logic_vector(31 downto 0);
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outbound_data : in std_logic_vector(31 downto 0);
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outbound_data_read : out std_logic;
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outbound_data_read : out std_logic;
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outbound_info : in std_logic_vector(15 downto 0);
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outbound_info : in std_logic_vector(15 downto 0);
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outbound_info_empty : in std_logic;
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outbound_info_empty : in std_logic;
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outbound_info_read : out std_logic;
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outbound_info_read : out std_logic;
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port_vlan_default : in std_logic_vector(15 downto 0);
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port_vlan_default : in std_logic_vector(15 downto 0);
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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tx_ff_uflow : in STD_LOGIC);
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tx_ff_uflow : in STD_LOGIC);
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end entity esoc_port_mal_outbound;
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end entity esoc_port_mal_outbound;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_port_mal_outbound.esoc_port_mal_outbound
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-- Object : Architecture work.esoc_port_mal_outbound.esoc_port_mal_outbound
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-- Last modified : Mon Apr 14 12:49:17 2014.
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-- Last modified : Mon Apr 14 12:49:17 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture esoc_port_mal_outbound of esoc_port_mal_outbound is
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architecture esoc_port_mal_outbound of esoc_port_mal_outbound is
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- registers
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-- registers
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- signals
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-- signals
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---------------------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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type ff_tx_states is (idle, running, drop);
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type ff_tx_states is (idle, running, drop);
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signal ff_tx_state: ff_tx_states;
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signal ff_tx_state: ff_tx_states;
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signal ff_tx_byte_counter: integer range 2**esoc_outbound_info_length_size-1 downto 0;
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signal ff_tx_byte_counter: integer range 2**esoc_outbound_info_length_size-1 downto 0;
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signal ff_tx_word_counter: integer range ((2**esoc_outbound_info_length_size)/4)-1 downto 0;
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signal ff_tx_word_counter: integer range ((2**esoc_outbound_info_length_size)/4)-1 downto 0;
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signal outbound_data_read_enable: std_logic;
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signal outbound_data_read_enable: std_logic;
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signal outbound_data_read_dummy: std_logic;
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signal outbound_data_read_dummy: std_logic;
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signal outbound_data_modify_enable: std_logic;
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signal outbound_data_modify_enable: std_logic;
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signal outbound_data_modify: std_logic_vector(outbound_data'high downto 0);
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signal outbound_data_modify: std_logic_vector(outbound_data'high downto 0);
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signal outbound_info_vlan_flag: std_logic;
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signal outbound_info_vlan_flag: std_logic;
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signal boundary64: std_logic;
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signal boundary64: std_logic;
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begin
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begin
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--=============================================================================================================
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--=============================================================================================================
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-- Process : capture and store data when ready acycle occurs
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-- Process : capture and store data when ready acycle occurs
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-- Description :
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-- Description :
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--=============================================================================================================
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--=============================================================================================================
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capture: process(clk_control, reset)
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capture: process(clk_control, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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ff_tx_sop <= '0';
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ff_tx_sop <= '0';
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ff_tx_eop <= '0';
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ff_tx_eop <= '0';
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ff_tx_wren <= '0';
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ff_tx_wren <= '0';
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ff_tx_mod <= (others => '0');
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ff_tx_mod <= (others => '0');
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ff_tx_byte_counter <= 0;
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ff_tx_byte_counter <= 0;
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ff_tx_word_counter <= 0;
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ff_tx_word_counter <= 0;
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outbound_info_vlan_flag <= '0';
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outbound_info_vlan_flag <= '0';
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outbound_data_modify_enable <= '0';
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outbound_data_modify_enable <= '0';
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outbound_data_modify <= (others => '0');
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outbound_data_modify <= (others => '0');
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outbound_info_read <= '0';
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outbound_info_read <= '0';
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outbound_data_read_dummy <= '0';
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outbound_data_read_dummy <= '0';
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outbound_data_read_enable <= '0';
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outbound_data_read_enable <= '0';
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boundary64 <= '0';
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boundary64 <= '0';
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elsif clk_control'event and clk_control = '1' then
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elsif clk_control'event and clk_control = '1' then
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-- clear one-clock active signals
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-- clear one-clock active signals
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outbound_info_read <= '0';
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outbound_info_read <= '0';
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outbound_data_read_dummy <= '0';
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outbound_data_read_dummy <= '0';
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outbound_data_modify_enable <= '0';
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outbound_data_modify_enable <= '0';
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case ff_tx_state is
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case ff_tx_state is
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when idle => -- create dummy read if the previous transaction does not end on a 64 bit boundary
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when idle => -- create dummy read if the previous transaction does not end on a 64 bit boundary
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if boundary64 = '1' then
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if boundary64 = '1' then
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boundary64 <= '0';
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boundary64 <= '0';
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outbound_data_read_dummy <= '1';
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outbound_data_read_dummy <= '1';
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-- Info fifo not empty? Get length from info fifo and acknowledge info fifo read! Start packet transmission.
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-- Info fifo not empty? Get length from info fifo and acknowledge info fifo read! Start packet transmission.
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elsif outbound_info_empty = '0' then
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elsif outbound_info_empty = '0' then
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-- get the length, subtract 4 byes because first word is provided on ST interface immediately, acknowledge info from fifo
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-- get the length, subtract 4 byes because first word is provided on ST interface immediately, acknowledge info from fifo
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outbound_info_read <= '1';
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outbound_info_read <= '1';
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ff_tx_word_counter <= 0;
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ff_tx_word_counter <= 0;
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ff_tx_byte_counter <= to_integer(unsigned(outbound_info(esoc_outbound_info_length+esoc_outbound_info_length_size-1 downto esoc_outbound_info_length)))-4;
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ff_tx_byte_counter <= to_integer(unsigned(outbound_info(esoc_outbound_info_length+esoc_outbound_info_length_size-1 downto esoc_outbound_info_length)))-4;
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outbound_info_vlan_flag <= outbound_info(esoc_outbound_info_vlan_flag);
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outbound_info_vlan_flag <= outbound_info(esoc_outbound_info_vlan_flag);
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-- send packet to MAC or drop packet if an error is indicated, error can be packet in data FIFO not complete due to overrun
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-- send packet to MAC or drop packet if an error is indicated, error can be packet in data FIFO not complete due to overrun
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if outbound_info(esoc_outbound_info_error_flag) = '0' then
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if outbound_info(esoc_outbound_info_error_flag) = '0' then
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outbound_data_read_enable <= '1';
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outbound_data_read_enable <= '1';
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ff_tx_sop <= '1';
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ff_tx_sop <= '1';
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ff_tx_wren <= '1';
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ff_tx_wren <= '1';
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ff_tx_state <= running;
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ff_tx_state <= running;
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-- receive data has an error, drop it!
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-- receive data has an error, drop it!
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else
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else
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outbound_data_read_dummy <= '1';
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outbound_data_read_dummy <= '1';
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ff_tx_state <= drop;
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ff_tx_state <= drop;
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end if;
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end if;
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end if;
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end if;
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when running => -- provide next data when ready is asserted (=acknowledge of current data)
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when running => -- provide next data when ready is asserted (=acknowledge of current data)
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if ff_tx_rdy = '1' then
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if ff_tx_rdy = '1' then
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--
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--
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-- CONTROL THE ST INTERFACE TO MAC
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-- CONTROL THE ST INTERFACE TO MAC
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--
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--
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-- deassert the start of packet
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-- deassert the start of packet
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ff_tx_sop <= '0';
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ff_tx_sop <= '0';
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-- last word of transaction read by ST Sink port, stop transfer
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-- last word of transaction read by ST Sink port, stop transfer
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if ff_tx_byte_counter = 0 then
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if ff_tx_byte_counter = 0 then
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outbound_data_read_enable <= '0';
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outbound_data_read_enable <= '0';
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ff_tx_eop <= '0';
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ff_tx_eop <= '0';
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ff_tx_wren <= '0';
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ff_tx_wren <= '0';
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ff_tx_state <= idle;
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ff_tx_state <= idle;
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-- last word of transaction to be read by ST Sink port?
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-- last word of transaction to be read by ST Sink port?
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elsif ff_tx_byte_counter <= 4 then
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elsif ff_tx_byte_counter <= 4 then
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ff_tx_eop <= '1';
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ff_tx_eop <= '1';
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ff_tx_byte_counter <= 0;
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ff_tx_byte_counter <= 0;
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ff_tx_mod <= std_logic_vector(to_unsigned(4-ff_tx_byte_counter,ff_tx_mod'length));
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ff_tx_mod <= std_logic_vector(to_unsigned(4-ff_tx_byte_counter,ff_tx_mod'length));
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-- transaction not finished, update counter
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-- transaction not finished, update counter
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else
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else
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ff_tx_byte_counter <= ff_tx_byte_counter - 4;
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ff_tx_byte_counter <= ff_tx_byte_counter - 4;
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end if;
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end if;
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-- toggle to know from which boundary is read, 32b or 64b
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-- toggle to know from which boundary is read, 32b or 64b
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boundary64 <= not(boundary64);
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boundary64 <= not(boundary64);
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--
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--
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-- MANIPULATE DATA
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-- MANIPULATE DATA
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--
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--
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-- modify vlan id with default vlan id if packet is tagged and force default vlan is enabled
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-- modify vlan id with default vlan id if packet is tagged and force default vlan is enabled
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if ff_tx_word_counter = 2 then
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if ff_tx_word_counter = 2 then
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if outbound_info_vlan_flag = '1' and force_vlan_default_out = '1' then
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if outbound_info_vlan_flag = '1' and force_vlan_default_out = '1' then
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outbound_data_modify_enable <= '1';
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outbound_data_modify_enable <= '1';
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outbound_data_modify <= esoc_ethernet_vlan_type & port_vlan_default;
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outbound_data_modify <= esoc_ethernet_vlan_type & port_vlan_default;
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end if;
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end if;
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end if;
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end if;
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ff_tx_word_counter <= ff_tx_word_counter + 1;
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ff_tx_word_counter <= ff_tx_word_counter + 1;
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end if;
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end if;
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when drop => -- read erroneous packet from FIFO and drop!
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when drop => -- read erroneous packet from FIFO and drop!
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-- size of packet always multiple of 8 bytes, no boundary64 mechanism required
|
-- size of packet always multiple of 8 bytes, no boundary64 mechanism required
|
if ff_tx_byte_counter <= 4 then
|
if ff_tx_byte_counter <= 4 then
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ff_tx_state <= idle;
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ff_tx_state <= idle;
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|
|
else
|
else
|
ff_tx_byte_counter <= ff_tx_byte_counter - 4;
|
ff_tx_byte_counter <= ff_tx_byte_counter - 4;
|
end if;
|
end if;
|
|
|
outbound_data_read_dummy <= '1';
|
outbound_data_read_dummy <= '1';
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|
|
when others => ff_tx_state <= idle;
|
when others => ff_tx_state <= idle;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
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|
|
ff_tx_err <= '0';
|
ff_tx_err <= '0';
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ff_tx_crc_fwd <= '0';
|
ff_tx_crc_fwd <= '0';
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ff_tx_data <= outbound_data when outbound_data_modify_enable = '0' else outbound_data_modify;
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ff_tx_data <= outbound_data when outbound_data_modify_enable = '0' else outbound_data_modify;
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outbound_data_read <= (ff_tx_rdy and outbound_data_read_enable) or outbound_data_read_dummy;
|
outbound_data_read <= (ff_tx_rdy and outbound_data_read_enable) or outbound_data_read_dummy;
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|
end architecture esoc_port_mal_outbound ; -- of esoc_port_mal_outbound
|
end architecture esoc_port_mal_outbound ; -- of esoc_port_mal_outbound
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