--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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--
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---- Ethernet Switch on Configurable Logic IP Core ----
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
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---- ----
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--
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---- This file is part of the ESoCL project ----
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-- Ease library : work
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---- http://www.opencores.org/cores/esoc/ ----
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-- HDL library : work
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---- ----
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-- Host name : S212065
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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-- User name : df768
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---- ----
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-- Time stamp : Tue Aug 19 08:05:18 2014
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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--
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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-- Designed by : L.Maarsen
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---- ----
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-- Company : LogiXA
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---- Author(s): L.Maarsen ----
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-- Project info : eSoC
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---- Bert Maarsen, lmaarsen@opencores.org ----
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--
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.esoc_port_processor_search
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-- Object : Entity work.esoc_port_processor_search
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-- Last modified : Mon Apr 14 12:49:39 2014.
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-- Last modified : Mon Apr 14 12:49:39 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee, std, work;
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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use work.package_esoc_configuration.all;
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entity esoc_port_processor_search is
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entity esoc_port_processor_search is
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generic(
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generic(
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esoc_port_nr : integer := 0);
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esoc_port_nr : integer := 0);
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port(
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port(
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clk_search : in std_logic;
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clk_search : in std_logic;
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inbound_header : in std_logic_vector(111 downto 0);
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inbound_header : in std_logic_vector(111 downto 0);
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inbound_header_empty : in std_logic;
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inbound_header_empty : in std_logic;
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inbound_header_read : out std_logic;
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inbound_header_read : out std_logic;
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inbound_vlan_member : in STD_LOGIC_VECTOR(0 downto 0);
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inbound_vlan_member : in STD_LOGIC_VECTOR(0 downto 0);
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reset : in std_logic;
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reset : in std_logic;
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search_data : out STD_LOGIC_VECTOR(15 downto 0);
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search_data : out STD_LOGIC_VECTOR(15 downto 0);
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search_done_cnt : out std_logic;
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search_done_cnt : out std_logic;
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search_drop_cnt : out std_logic;
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search_drop_cnt : out std_logic;
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search_eof : out std_logic;
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search_eof : out std_logic;
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search_gnt_wr : in std_logic;
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search_gnt_wr : in std_logic;
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search_key : out std_logic_vector(63 downto 0);
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search_key : out std_logic_vector(63 downto 0);
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search_req : out std_logic;
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search_req : out std_logic;
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search_result : in std_logic_vector(esoc_port_count-1 downto 0);
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search_result : in std_logic_vector(esoc_port_count-1 downto 0);
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search_result_av : in std_logic;
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search_result_av : in std_logic;
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search_sof : out std_logic;
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search_sof : out std_logic;
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search_write : out STD_LOGIC);
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search_write : out STD_LOGIC);
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end entity esoc_port_processor_search;
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end entity esoc_port_processor_search;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_port_processor_search.esoc_port_processor_search
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-- Object : Architecture work.esoc_port_processor_search.esoc_port_processor_search
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-- Last modified : Mon Apr 14 12:49:39 2014.
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-- Last modified : Mon Apr 14 12:49:39 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture esoc_port_processor_search of esoc_port_processor_search is
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architecture esoc_port_processor_search of esoc_port_processor_search is
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type search_states is (idle, send_key_1, send_key_2, wait_for_result);
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type search_states is (idle, send_key_1, send_key_2, wait_for_result);
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signal search_state: search_states;
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signal search_state: search_states;
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signal search_sof_o: std_logic;
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signal search_sof_o: std_logic;
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signal search_eof_o: std_logic;
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signal search_eof_o: std_logic;
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signal search_key_o: std_logic_vector(search_key'high downto 0);
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signal search_key_o: std_logic_vector(search_key'high downto 0);
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signal inbound_header_empty_i: std_logic;
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signal inbound_header_empty_i: std_logic;
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begin
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begin
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-- control the shared bus to the search engine
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-- control the shared bus to the search engine
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search_sof <= search_sof_o when search_gnt_wr = '1' else 'Z';
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search_sof <= search_sof_o when search_gnt_wr = '1' else 'Z';
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search_eof <= search_eof_o when search_gnt_wr = '1' else 'Z';
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search_eof <= search_eof_o when search_gnt_wr = '1' else 'Z';
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search_key <= search_key_o when search_gnt_wr = '1' else (others => 'Z');
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search_key <= search_key_o when search_gnt_wr = '1' else (others => 'Z');
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--=============================================================================================================
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--=============================================================================================================
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-- Process :
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-- Process :
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-- Description :
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-- Description :
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--=============================================================================================================
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--=============================================================================================================
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debug: process(clk_search, reset)
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debug: process(clk_search, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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inbound_header_read <= '0';
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inbound_header_read <= '0';
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inbound_header_empty_i <= '0';
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inbound_header_empty_i <= '0';
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search_req <= '0';
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search_req <= '0';
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search_sof_o <= '0';
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search_sof_o <= '0';
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search_eof_o <= '0';
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search_eof_o <= '0';
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search_key_o <= (others => '0');
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search_key_o <= (others => '0');
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search_data <= (others => '0');
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search_data <= (others => '0');
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search_write <= '0';
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search_write <= '0';
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search_done_cnt <= '0';
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search_done_cnt <= '0';
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search_drop_cnt <= '0';
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search_drop_cnt <= '0';
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search_state <= idle;
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search_state <= idle;
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elsif clk_search'event and clk_search = '1' then
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elsif clk_search'event and clk_search = '1' then
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-- reset one clock active signals
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-- reset one clock active signals
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search_eof_o <= '0';
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search_eof_o <= '0';
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search_done_cnt <= '0';
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search_done_cnt <= '0';
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search_drop_cnt <= '0';
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search_drop_cnt <= '0';
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search_write <= '0';
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search_write <= '0';
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inbound_header_read <= '0';
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inbound_header_read <= '0';
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-- delay the empty signal to proces the VLAN membership of the first packet correctly. When the header
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-- delay the empty signal to proces the VLAN membership of the first packet correctly. When the header
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-- data of first packet is written in de header FIFO the empty signal deasserts, but in parallel (outside
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-- data of first packet is written in de header FIFO the empty signal deasserts, but in parallel (outside
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-- this entity) the VLAN ID RAM is addressed. This entity detects the deasserted EMTPY signal and expects
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-- this entity) the VLAN ID RAM is addressed. This entity detects the deasserted EMTPY signal and expects
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-- the corresponding VLAN membership info from the VLAN ID RAM, which is not available at that time!
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-- the corresponding VLAN membership info from the VLAN ID RAM, which is not available at that time!
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-- This is only applicable if the first header in the FIFO is from a tagged packet and the EMPTY latency of the
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-- This is only applicable if the first header in the FIFO is from a tagged packet and the EMPTY latency of the
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-- FIFO is 0, the latter is not the case for Altera, so you can skip this delay by using the inbound_header_empty
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-- FIFO is 0, the latter is not the case for Altera, so you can skip this delay by using the inbound_header_empty
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-- iso. the inbound_header_empty_i signal in the search_state idle .... check simulation!
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-- iso. the inbound_header_empty_i signal in the search_state idle .... check simulation!
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inbound_header_empty_i <= inbound_header_empty;
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inbound_header_empty_i <= inbound_header_empty;
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case search_state is
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case search_state is
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when idle => -- used to insert a clock delay
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when idle => -- used to insert a clock delay
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search_state <= send_key_1;
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search_state <= send_key_1;
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when send_key_1 => -- check for new header data,new header data means new packet is coming or already available
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when send_key_1 => -- check for new header data,new header data means new packet is coming or already available
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if inbound_header_empty = '0' then
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if inbound_header_empty = '0' then
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-- Is the inbound port member of the VID of the tagged packet or
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-- Is the inbound port member of the VID of the tagged packet or
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-- is the packet untagged and does the switch use the port default VID?
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-- is the packet untagged and does the switch use the port default VID?
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if inbound_header(esoc_inbound_header_vlan_flag) = '0' or inbound_vlan_member = "1" then
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if inbound_header(esoc_inbound_header_vlan_flag) = '0' or inbound_vlan_member = "1" then
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-- Request bus to the search engine, prepare to transfer VID and DA
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-- Request bus to the search engine, prepare to transfer VID and DA
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search_req <= '1';
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search_req <= '1';
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search_sof_o <= '1';
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search_sof_o <= '1';
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search_key_o(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan) <= inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan);
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search_key_o(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan) <= inbound_header(esoc_inbound_header_vlan+11 downto esoc_inbound_header_vlan);
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search_key_o(esoc_search_bus_mac+47 downto esoc_search_bus_mac) <= inbound_header(esoc_inbound_header_dmac_lo+47 downto esoc_inbound_header_dmac_lo);
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search_key_o(esoc_search_bus_mac+47 downto esoc_search_bus_mac) <= inbound_header(esoc_inbound_header_dmac_lo+47 downto esoc_inbound_header_dmac_lo);
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search_state <= send_key_2;
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search_state <= send_key_2;
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-- Packet is tagged and the inbound port is not member of the packet VID
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-- Packet is tagged and the inbound port is not member of the packet VID
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else
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else
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-- Write destination port (none) and acknowledge header data
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-- Write destination port (none) and acknowledge header data
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search_data <= (others => '0');
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search_data <= (others => '0');
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search_write <= '1';
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search_write <= '1';
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inbound_header_read <= '1';
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inbound_header_read <= '1';
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search_drop_cnt <= '1';
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search_drop_cnt <= '1';
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search_state <= idle;
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search_state <= idle;
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end if;
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end if;
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end if;
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end if;
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when send_key_2 => -- VID and DA Address accepted when granted, provide Port Number and SA Address for learning process
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when send_key_2 => -- VID and DA Address accepted when granted, provide Port Number and SA Address for learning process
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if search_gnt_wr = '1' then
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if search_gnt_wr = '1' then
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search_key_o(esoc_search_bus_sport+15 downto esoc_search_bus_sport) <= (others => '0');
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search_key_o(esoc_search_bus_sport+15 downto esoc_search_bus_sport) <= (others => '0');
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search_key_o(esoc_search_bus_sport+esoc_port_nr) <= '1';
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search_key_o(esoc_search_bus_sport+esoc_port_nr) <= '1';
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search_key_o(esoc_search_bus_mac+47 downto esoc_search_bus_mac) <= inbound_header(esoc_inbound_header_smac_lo+47 downto esoc_inbound_header_smac_lo);
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search_key_o(esoc_search_bus_mac+47 downto esoc_search_bus_mac) <= inbound_header(esoc_inbound_header_smac_lo+47 downto esoc_inbound_header_smac_lo);
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search_sof_o <= '0';
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search_sof_o <= '0';
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inbound_header_read <= '1';
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inbound_header_read <= '1';
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search_state <= wait_for_result;
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search_state <= wait_for_result;
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end if;
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end if;
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when wait_for_result => -- Wait for result from search engine
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when wait_for_result => -- Wait for result from search engine
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if search_result_av = '1' then
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if search_result_av = '1' then
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-- Write destination ports, skip your self, acknowledge header data
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-- Write destination ports, skip your self, acknowledge header data
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search_data(search_result'high downto 0) <= search_result;
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search_data(search_result'high downto 0) <= search_result;
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search_data(esoc_port_nr) <= '0';
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search_data(esoc_port_nr) <= '0';
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search_write <= '1';
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search_write <= '1';
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search_done_cnt <= '1';
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search_done_cnt <= '1';
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search_req <= '0';
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search_req <= '0';
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search_eof_o <= '1';
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search_eof_o <= '1';
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search_state <= send_key_1;
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search_state <= send_key_1;
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end if;
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end if;
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when others => search_state <= idle;
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when others => search_state <= idle;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end architecture esoc_port_processor_search ; -- of esoc_port_processor_search
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end architecture esoc_port_processor_search ; -- of esoc_port_processor_search
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