--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
---- ----
|
--
|
---- Ethernet Switch on Configurable Logic IP Core ----
|
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
|
---- ----
|
--
|
---- This file is part of the ESoCL project ----
|
-- Ease library : work
|
---- http://www.opencores.org/cores/esoc/ ----
|
-- HDL library : work
|
---- ----
|
-- Host name : S212065
|
---- Description: see design description ESoCL_dd_71022001.pdf ----
|
-- User name : df768
|
---- ----
|
-- Time stamp : Tue Aug 19 08:05:18 2014
|
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
|
--
|
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
|
-- Designed by : L.Maarsen
|
---- ----
|
-- Company : LogiXA
|
---- Author(s): L.Maarsen ----
|
-- Project info : eSoC
|
---- Bert Maarsen, lmaarsen@opencores.org ----
|
--
|
---- ----
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
---- ----
|
|
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
|
|
---- ----
|
|
---- This source file may be used and distributed without ----
|
|
---- restriction provided that this copyright statement is not ----
|
|
---- removed from the file and that any derivative work contains ----
|
|
---- the original copyright notice and the associated disclaimer. ----
|
|
---- ----
|
|
---- This source file is free software; you can redistribute it ----
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
|
---- Public License as published by the Free Software Foundation; ----
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
|
---- later version. ----
|
|
---- ----
|
|
---- This source is distributed in the hope that it will be ----
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
|
---- details. ----
|
|
---- ----
|
|
---- You should have received a copy of the GNU Lesser General ----
|
|
---- Public License along with this source; if not, download it ----
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
|
---- ----
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Object : Entity work.esoc_port_storage
|
-- Object : Entity work.esoc_port_storage
|
-- Last modified : Mon Apr 14 12:49:43 2014.
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-- Last modified : Mon Apr 14 12:49:43 2014.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
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library ieee, std, work;
|
library ieee, std, work;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use std.textio.all;
|
use std.textio.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.package_esoc_configuration.all;
|
use work.package_esoc_configuration.all;
|
|
|
entity esoc_port_storage is
|
entity esoc_port_storage is
|
port(
|
port(
|
clk_control : in std_logic;
|
clk_control : in std_logic;
|
clk_data : in std_logic;
|
clk_data : in std_logic;
|
clk_search : in std_logic;
|
clk_search : in std_logic;
|
inbound_port_data : in std_logic_vector(31 downto 0);
|
inbound_port_data : in std_logic_vector(31 downto 0);
|
inbound_port_data_full : out std_logic;
|
inbound_port_data_full : out std_logic;
|
inbound_port_data_write : in std_logic;
|
inbound_port_data_write : in std_logic;
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inbound_port_header : in std_logic_vector(111 downto 0);
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inbound_port_header : in std_logic_vector(111 downto 0);
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inbound_port_header_write : in std_logic;
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inbound_port_header_write : in std_logic;
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inbound_port_info : in std_logic_vector(31 downto 0);
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inbound_port_info : in std_logic_vector(31 downto 0);
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inbound_port_info_write : in std_logic;
|
inbound_port_info_write : in std_logic;
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inbound_proc_data : out std_logic_vector(63 downto 0);
|
inbound_proc_data : out std_logic_vector(63 downto 0);
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inbound_proc_data_full : out std_logic;
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inbound_proc_data_full : out std_logic;
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inbound_proc_data_read : in std_logic;
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inbound_proc_data_read : in std_logic;
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inbound_proc_header : out std_logic_vector(111 downto 0);
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inbound_proc_header : out std_logic_vector(111 downto 0);
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inbound_proc_header_empty : out std_logic;
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inbound_proc_header_empty : out std_logic;
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inbound_proc_header_read : in std_logic;
|
inbound_proc_header_read : in std_logic;
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inbound_proc_info : out std_logic_vector(31 downto 0);
|
inbound_proc_info : out std_logic_vector(31 downto 0);
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inbound_proc_info_empty : out std_logic;
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inbound_proc_info_empty : out std_logic;
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inbound_proc_info_read : in std_logic;
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inbound_proc_info_read : in std_logic;
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outbound_port_data : out std_logic_vector(31 downto 0);
|
outbound_port_data : out std_logic_vector(31 downto 0);
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outbound_port_data_read : in std_logic;
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outbound_port_data_read : in std_logic;
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outbound_port_info : out std_logic_vector(15 downto 0);
|
outbound_port_info : out std_logic_vector(15 downto 0);
|
outbound_port_info_empty : out std_logic;
|
outbound_port_info_empty : out std_logic;
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outbound_port_info_read : in std_logic;
|
outbound_port_info_read : in std_logic;
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outbound_proc_data : in std_logic_vector(63 downto 0);
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outbound_proc_data : in std_logic_vector(63 downto 0);
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outbound_proc_data_full : out std_logic;
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outbound_proc_data_full : out std_logic;
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outbound_proc_data_write : in std_logic;
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outbound_proc_data_write : in std_logic;
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outbound_proc_info : in std_logic_vector(15 downto 0);
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outbound_proc_info : in std_logic_vector(15 downto 0);
|
outbound_proc_info_write : in std_logic;
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outbound_proc_info_write : in std_logic;
|
reset : in std_logic);
|
reset : in std_logic);
|
end entity esoc_port_storage;
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end entity esoc_port_storage;
|
|
|
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_port_storage.structure
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-- Object : Architecture work.esoc_port_storage.structure
|
-- Last modified : Mon Apr 14 12:49:43 2014.
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-- Last modified : Mon Apr 14 12:49:43 2014.
|
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture structure of esoc_port_storage is
|
architecture structure of esoc_port_storage is
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|
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signal inbound_wrusedw : STD_LOGIC_VECTOR(10 downto 0);
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signal inbound_wrusedw : STD_LOGIC_VECTOR(10 downto 0);
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signal inbound_rdusedw : STD_LOGIC_VECTOR(9 downto 0);
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signal inbound_rdusedw : STD_LOGIC_VECTOR(9 downto 0);
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|
|
component esoc_fifo_256x32
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component esoc_fifo_256x32
|
port(
|
port(
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aclr : in STD_LOGIC := '0';
|
aclr : in STD_LOGIC := '0';
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data : in STD_LOGIC_VECTOR(31 downto 0);
|
data : in STD_LOGIC_VECTOR(31 downto 0);
|
rdclk : in STD_LOGIC;
|
rdclk : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
q : out STD_LOGIC_VECTOR(31 downto 0);
|
q : out STD_LOGIC_VECTOR(31 downto 0);
|
rdempty : out STD_LOGIC;
|
rdempty : out STD_LOGIC;
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rdusedw : out STD_LOGIC_VECTOR(7 downto 0);
|
rdusedw : out STD_LOGIC_VECTOR(7 downto 0);
|
wrfull : out STD_LOGIC;
|
wrfull : out STD_LOGIC;
|
wrusedw : out STD_LOGIC_VECTOR(7 downto 0));
|
wrusedw : out STD_LOGIC_VECTOR(7 downto 0));
|
end component esoc_fifo_256x32;
|
end component esoc_fifo_256x32;
|
|
|
component esoc_fifo_256x112
|
component esoc_fifo_256x112
|
port(
|
port(
|
aclr : in STD_LOGIC := '0';
|
aclr : in STD_LOGIC := '0';
|
data : in STD_LOGIC_VECTOR(111 downto 0);
|
data : in STD_LOGIC_VECTOR(111 downto 0);
|
rdclk : in STD_LOGIC;
|
rdclk : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
q : out STD_LOGIC_VECTOR(111 downto 0);
|
q : out STD_LOGIC_VECTOR(111 downto 0);
|
rdempty : out STD_LOGIC;
|
rdempty : out STD_LOGIC;
|
rdusedw : out STD_LOGIC_VECTOR(7 downto 0);
|
rdusedw : out STD_LOGIC_VECTOR(7 downto 0);
|
wrfull : out STD_LOGIC;
|
wrfull : out STD_LOGIC;
|
wrusedw : out STD_LOGIC_VECTOR(7 downto 0));
|
wrusedw : out STD_LOGIC_VECTOR(7 downto 0));
|
end component esoc_fifo_256x112;
|
end component esoc_fifo_256x112;
|
|
|
component esoc_fifo_256x16
|
component esoc_fifo_256x16
|
port(
|
port(
|
aclr : in STD_LOGIC := '0';
|
aclr : in STD_LOGIC := '0';
|
data : in STD_LOGIC_VECTOR(15 downto 0);
|
data : in STD_LOGIC_VECTOR(15 downto 0);
|
rdclk : in STD_LOGIC;
|
rdclk : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
q : out STD_LOGIC_VECTOR(15 downto 0);
|
q : out STD_LOGIC_VECTOR(15 downto 0);
|
rdempty : out STD_LOGIC;
|
rdempty : out STD_LOGIC;
|
rdusedw : out STD_LOGIC_VECTOR(7 downto 0);
|
rdusedw : out STD_LOGIC_VECTOR(7 downto 0);
|
wrfull : out STD_LOGIC;
|
wrfull : out STD_LOGIC;
|
wrusedw : out STD_LOGIC_VECTOR(7 downto 0));
|
wrusedw : out STD_LOGIC_VECTOR(7 downto 0));
|
end component esoc_fifo_256x16;
|
end component esoc_fifo_256x16;
|
|
|
component esoc_fifo_2kx32x64
|
component esoc_fifo_2kx32x64
|
port(
|
port(
|
aclr : in STD_LOGIC := '0';
|
aclr : in STD_LOGIC := '0';
|
data : in STD_LOGIC_VECTOR(31 downto 0);
|
data : in STD_LOGIC_VECTOR(31 downto 0);
|
rdclk : in STD_LOGIC;
|
rdclk : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
q : out STD_LOGIC_VECTOR(63 downto 0);
|
q : out STD_LOGIC_VECTOR(63 downto 0);
|
rdempty : out STD_LOGIC;
|
rdempty : out STD_LOGIC;
|
rdusedw : out STD_LOGIC_VECTOR(9 downto 0);
|
rdusedw : out STD_LOGIC_VECTOR(9 downto 0);
|
wrfull : out STD_LOGIC;
|
wrfull : out STD_LOGIC;
|
wrusedw : out STD_LOGIC_VECTOR(10 downto 0));
|
wrusedw : out STD_LOGIC_VECTOR(10 downto 0));
|
end component esoc_fifo_2kx32x64;
|
end component esoc_fifo_2kx32x64;
|
|
|
component esoc_fifo_2kx64x32
|
component esoc_fifo_2kx64x32
|
port(
|
port(
|
aclr : in STD_LOGIC := '0';
|
aclr : in STD_LOGIC := '0';
|
data : in STD_LOGIC_VECTOR(63 downto 0);
|
data : in STD_LOGIC_VECTOR(63 downto 0);
|
rdclk : in STD_LOGIC;
|
rdclk : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
rdreq : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrclk : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
wrreq : in STD_LOGIC;
|
q : out STD_LOGIC_VECTOR(31 downto 0);
|
q : out STD_LOGIC_VECTOR(31 downto 0);
|
rdempty : out STD_LOGIC;
|
rdempty : out STD_LOGIC;
|
rdusedw : out STD_LOGIC_VECTOR(10 downto 0);
|
rdusedw : out STD_LOGIC_VECTOR(10 downto 0);
|
wrfull : out STD_LOGIC;
|
wrfull : out STD_LOGIC;
|
wrusedw : out STD_LOGIC_VECTOR(9 downto 0));
|
wrusedw : out STD_LOGIC_VECTOR(9 downto 0));
|
end component esoc_fifo_2kx64x32;
|
end component esoc_fifo_2kx64x32;
|
|
|
begin
|
begin
|
--Inbound FIFO's
|
--Inbound FIFO's
|
--- Data Fifo
|
--- Data Fifo
|
--- Info Fifo
|
--- Info Fifo
|
--- Header Fifo
|
--- Header Fifo
|
--Outbound FIFO's
|
--Outbound FIFO's
|
--- Data Fifo
|
--- Data Fifo
|
--- Info Fifo
|
--- Info Fifo
|
u1: esoc_fifo_256x32
|
u1: esoc_fifo_256x32
|
port map(
|
port map(
|
aclr => reset,
|
aclr => reset,
|
data => inbound_port_info,
|
data => inbound_port_info,
|
rdclk => clk_data,
|
rdclk => clk_data,
|
rdreq => inbound_proc_info_read,
|
rdreq => inbound_proc_info_read,
|
wrclk => clk_control,
|
wrclk => clk_control,
|
wrreq => inbound_port_info_write,
|
wrreq => inbound_port_info_write,
|
q => inbound_proc_info,
|
q => inbound_proc_info,
|
rdempty => inbound_proc_info_empty,
|
rdempty => inbound_proc_info_empty,
|
rdusedw => open,
|
rdusedw => open,
|
wrfull => open,
|
wrfull => open,
|
wrusedw => open);
|
wrusedw => open);
|
|
|
u4: esoc_fifo_256x112
|
u4: esoc_fifo_256x112
|
port map(
|
port map(
|
aclr => reset,
|
aclr => reset,
|
data => inbound_port_header,
|
data => inbound_port_header,
|
rdclk => clk_search,
|
rdclk => clk_search,
|
rdreq => inbound_proc_header_read,
|
rdreq => inbound_proc_header_read,
|
wrclk => clk_control,
|
wrclk => clk_control,
|
wrreq => inbound_port_header_write,
|
wrreq => inbound_port_header_write,
|
q => inbound_proc_header,
|
q => inbound_proc_header,
|
rdempty => inbound_proc_header_empty,
|
rdempty => inbound_proc_header_empty,
|
rdusedw => open,
|
rdusedw => open,
|
wrfull => open,
|
wrfull => open,
|
wrusedw => open);
|
wrusedw => open);
|
|
|
u5: esoc_fifo_256x16
|
u5: esoc_fifo_256x16
|
port map(
|
port map(
|
aclr => reset,
|
aclr => reset,
|
data => outbound_proc_info,
|
data => outbound_proc_info,
|
rdclk => clk_control,
|
rdclk => clk_control,
|
rdreq => outbound_port_info_read,
|
rdreq => outbound_port_info_read,
|
wrclk => clk_data,
|
wrclk => clk_data,
|
wrreq => outbound_proc_info_write,
|
wrreq => outbound_proc_info_write,
|
q => outbound_port_info,
|
q => outbound_port_info,
|
rdempty => outbound_port_info_empty,
|
rdempty => outbound_port_info_empty,
|
rdusedw => open,
|
rdusedw => open,
|
wrfull => open,
|
wrfull => open,
|
wrusedw => open);
|
wrusedw => open);
|
|
|
u6: esoc_fifo_2kx32x64
|
u6: esoc_fifo_2kx32x64
|
port map(
|
port map(
|
aclr => reset,
|
aclr => reset,
|
data => inbound_port_data,
|
data => inbound_port_data,
|
rdclk => clk_data,
|
rdclk => clk_data,
|
rdreq => inbound_proc_data_read,
|
rdreq => inbound_proc_data_read,
|
wrclk => clk_control,
|
wrclk => clk_control,
|
wrreq => inbound_port_data_write,
|
wrreq => inbound_port_data_write,
|
q => inbound_proc_data,
|
q => inbound_proc_data,
|
rdempty => open,
|
rdempty => open,
|
rdusedw => inbound_rdusedw,
|
rdusedw => inbound_rdusedw,
|
wrfull => open,
|
wrfull => open,
|
wrusedw => inbound_wrusedw);
|
wrusedw => inbound_wrusedw);
|
|
|
u0: esoc_fifo_2kx64x32
|
u0: esoc_fifo_2kx64x32
|
port map(
|
port map(
|
aclr => reset,
|
aclr => reset,
|
data => outbound_proc_data,
|
data => outbound_proc_data,
|
rdclk => clk_control,
|
rdclk => clk_control,
|
rdreq => outbound_port_data_read,
|
rdreq => outbound_port_data_read,
|
wrclk => clk_data,
|
wrclk => clk_data,
|
wrreq => outbound_proc_data_write,
|
wrreq => outbound_proc_data_write,
|
q => outbound_port_data,
|
q => outbound_port_data,
|
rdempty => open,
|
rdempty => open,
|
rdusedw => open,
|
rdusedw => open,
|
wrfull => outbound_proc_data_full,
|
wrfull => outbound_proc_data_full,
|
wrusedw => open);
|
wrusedw => open);
|
|
|
|
|
-- FIFO Behaviour: ST to Write FIFO latency is 1 clock cycle, take this into account
|
-- FIFO Behaviour: ST to Write FIFO latency is 1 clock cycle, take this into account
|
-- WRUSEDW latency is 1 clock cycle, take this into account
|
-- WRUSEDW latency is 1 clock cycle, take this into account
|
-- WRUSEDW becomes 2047 -> 0 when FIFO is completely full, take this into account
|
-- WRUSEDW becomes 2047 -> 0 when FIFO is completely full, take this into account
|
-- WRUSEDW must end on an even number of words due to 32/64 conversion, take this into account
|
-- WRUSEDW must end on an even number of words due to 32/64 conversion, take this into account
|
-- Conclusion: set Almost Full threshold offset on 3
|
-- Conclusion: set Almost Full threshold offset on 3
|
--
|
--
|
-- Ready Latency @ ST Interface is 2
|
-- Ready Latency @ ST Interface is 2
|
--
|
--
|
-- Required Almost Full threshold: 1 + 1 + 1 + 1 + 2 = 6
|
-- Required Almost Full threshold: 1 + 1 + 1 + 1 + 2 = 6
|
--
|
--
|
inbound_port_data_full <= '1' when (2**inbound_wrusedw'length - to_integer(unsigned(inbound_wrusedw))) <= 6 else '0';
|
inbound_port_data_full <= '1' when (2**inbound_wrusedw'length - to_integer(unsigned(inbound_wrusedw))) <= 6 else '0';
|
|
|
--
|
--
|
inbound_proc_data_full <= '1' when to_integer(unsigned(inbound_rdusedw)) = ((2**inbound_rdusedw'length)-1) else '0';
|
inbound_proc_data_full <= '1' when to_integer(unsigned(inbound_rdusedw)) = ((2**inbound_rdusedw'length)-1) else '0';
|
end architecture structure ; -- of esoc_port_storage
|
end architecture structure ; -- of esoc_port_storage
|
|
|
|
|