--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
---- ----
|
--
|
---- Ethernet Switch on Configurable Logic IP Core ----
|
-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
|
---- ----
|
--
|
---- This file is part of the ESoCL project ----
|
-- Ease library : work
|
---- http://www.opencores.org/cores/esoc/ ----
|
-- HDL library : work
|
---- ----
|
-- Host name : S212065
|
---- Description: see design description ESoCL_dd_71022001.pdf ----
|
-- User name : df768
|
---- ----
|
-- Time stamp : Tue Aug 19 08:05:18 2014
|
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
|
--
|
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
|
-- Designed by : L.Maarsen
|
---- ----
|
-- Company : LogiXA
|
---- Author(s): L.Maarsen ----
|
-- Project info : eSoC
|
---- Bert Maarsen, lmaarsen@opencores.org ----
|
--
|
---- ----
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
---- ----
|
|
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
|
|
---- ----
|
|
---- This source file may be used and distributed without ----
|
|
---- restriction provided that this copyright statement is not ----
|
|
---- removed from the file and that any derivative work contains ----
|
|
---- the original copyright notice and the associated disclaimer. ----
|
|
---- ----
|
|
---- This source file is free software; you can redistribute it ----
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
|
---- Public License as published by the Free Software Foundation; ----
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
|
---- later version. ----
|
|
---- ----
|
|
---- This source is distributed in the hope that it will be ----
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
|
---- details. ----
|
|
---- ----
|
|
---- You should have received a copy of the GNU Lesser General ----
|
|
---- Public License along with this source; if not, download it ----
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
|
---- ----
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Object : Entity work.esoc_search_engine_sa_store
|
-- Object : Entity work.esoc_search_engine_sa_store
|
-- Last modified : Mon Apr 14 12:50:14 2014.
|
-- Last modified : Tue Aug 19 08:05:17 2014.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
library ieee, std, work;
|
library ieee, std, work;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use std.textio.all;
|
use std.textio.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.package_esoc_configuration.all;
|
use work.package_esoc_configuration.all;
|
|
|
entity esoc_search_engine_sa_store is
|
entity esoc_search_engine_sa_store is
|
port(
|
port(
|
clk_search : in std_logic;
|
clk_search : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
search_eof : in std_logic;
|
search_eof : in std_logic;
|
search_key : in std_logic_vector(63 downto 0);
|
search_key : in std_logic_vector(63 downto 0);
|
search_sa_overload_cnt : out std_logic;
|
search_sa_overload_cnt : out std_logic;
|
search_sa_store_d : out STD_LOGIC_VECTOR(79 downto 0);
|
search_sa_store_d : out STD_LOGIC_VECTOR(79 downto 0);
|
search_sa_store_full : in STD_LOGIC;
|
search_sa_store_full : in STD_LOGIC;
|
search_sa_store_wr : out STD_LOGIC;
|
search_sa_store_wr : out STD_LOGIC;
|
search_sof : in std_logic);
|
search_sof : in std_logic);
|
end entity esoc_search_engine_sa_store;
|
end entity esoc_search_engine_sa_store;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Object : Architecture work.esoc_search_engine_sa_store.esoc_search_engine_sa_store
|
-- Object : Architecture work.esoc_search_engine_sa_store.esoc_search_engine_sa_store
|
-- Last modified : Mon Apr 14 12:50:14 2014.
|
-- Last modified : Tue Aug 19 08:05:17 2014.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
architecture esoc_search_engine_sa_store of esoc_search_engine_sa_store is
|
architecture esoc_search_engine_sa_store of esoc_search_engine_sa_store is
|
|
|
type store_sa_states is (idle, wait_sa, wait_full);
|
type store_sa_states is (idle, wait_sa, wait_full);
|
signal store_sa_state: store_sa_states;
|
signal store_sa_state: store_sa_states;
|
|
|
begin
|
begin
|
|
|
--=============================================================================================================
|
--=============================================================================================================
|
-- Process : proces store SA address for further processing
|
-- Process : proces store SA address for further processing
|
-- Description :
|
-- Description :
|
--=============================================================================================================
|
--=============================================================================================================
|
store_sa: process(clk_search, reset)
|
store_sa: process(clk_search, reset)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
search_sa_store_wr <= '0';
|
search_sa_store_wr <= '0';
|
search_sa_store_d <= (others => '0');
|
search_sa_store_d <= (others => '0');
|
search_sa_overload_cnt <= '0';
|
search_sa_overload_cnt <= '0';
|
store_sa_state <= idle;
|
store_sa_state <= idle;
|
|
|
elsif clk_search'event and clk_search = '1' then
|
elsif clk_search'event and clk_search = '1' then
|
-- clear one-clock active signals
|
-- clear one-clock active signals
|
search_sa_store_wr <= '0';
|
search_sa_store_wr <= '0';
|
search_sa_overload_cnt <= '0';
|
search_sa_overload_cnt <= '0';
|
|
|
-- define unused bits to avoid inferred latch warning during analysis & synthesis
|
-- define unused bits to avoid inferred latch warning during analysis & synthesis
|
search_sa_store_d(esoc_search_entry_valid) <= '0';
|
search_sa_store_d(esoc_search_entry_valid) <= '0';
|
search_sa_store_d(esoc_search_entry_update) <= '0';
|
search_sa_store_d(esoc_search_entry_aging) <= '0';
|
search_sa_store_d(esoc_search_entry_unused2 downto esoc_search_entry_unused1) <= (others => '0');
|
search_sa_store_d(esoc_search_entry_unused2 downto esoc_search_entry_unused1) <= (others => '0');
|
|
|
case store_sa_state is
|
case store_sa_state is
|
when idle => -- wait for start of frame, first data is VID + DA, skip DA, store VID, wait for SA and port number ... report when storage is full!
|
when idle => -- wait for start of frame, first data is VID + DA, skip DA, store VID, wait for SA and port number ... report when storage is full!
|
if search_sof = '1' then
|
if search_sof = '1' then
|
if search_sa_store_full = '0' then
|
if search_sa_store_full = '0' then
|
search_sa_store_d(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) <= search_key(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan);
|
search_sa_store_d(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) <= search_key(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan);
|
store_sa_state <= wait_sa;
|
store_sa_state <= wait_sa;
|
else
|
else
|
search_sa_overload_cnt <= '1';
|
search_sa_overload_cnt <= '1';
|
store_sa_state <= wait_full;
|
store_sa_state <= wait_full;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when wait_sa => -- get Source Port + SA and calculate hash pointer (additional delay may be required after synthesis, due to large XOR tree)
|
when wait_sa => -- get Source Port + SA and calculate hash pointer (additional delay may be required after synthesis, due to large XOR tree)
|
search_sa_store_d(esoc_search_entry_destination+15 downto esoc_search_entry_destination) <= search_key(esoc_search_bus_sport+15 downto esoc_search_bus_sport);
|
search_sa_store_d(esoc_search_entry_destination+15 downto esoc_search_entry_destination) <= search_key(esoc_search_bus_sport+15 downto esoc_search_bus_sport);
|
search_sa_store_d(esoc_search_entry_mac+47 downto esoc_search_entry_mac) <= search_key(esoc_search_bus_mac+47 downto esoc_search_bus_mac);
|
search_sa_store_d(esoc_search_entry_mac+47 downto esoc_search_entry_mac) <= search_key(esoc_search_bus_mac+47 downto esoc_search_bus_mac);
|
search_sa_store_wr <= '1';
|
search_sa_store_wr <= '1';
|
store_sa_state <= idle;
|
store_sa_state <= idle;
|
|
|
when wait_full => if search_sa_store_full = '0' then
|
when wait_full => if search_sa_store_full = '0' then
|
store_sa_state <= idle;
|
store_sa_state <= idle;
|
end if;
|
end if;
|
|
|
when others => store_sa_state <= idle;
|
when others => store_sa_state <= idle;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
end architecture esoc_search_engine_sa_store ; -- of esoc_search_engine_sa_store
|
end architecture esoc_search_engine_sa_store ; -- of esoc_search_engine_sa_store
|
|
|
|
|
