`timescale 1 ns/100ps
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`timescale 1 ns/100ps
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_top.v ////
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//// tb_top.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
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//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// replaced tab with space.
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// replaced tab with space.
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// passed 9.6k length frame test.
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// passed 9.6k length frame test.
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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// no message
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//
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//
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module tb_top (
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module tb_top (
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);
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);
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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//system signals
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//system signals
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reg Reset ;
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reg Reset ;
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reg Clk_125M ;
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reg Clk_125M ;
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reg Clk_user ;
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reg Clk_user ;
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reg Clk_reg ;
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reg Clk_reg ;
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//user interface
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//user interface
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wire Rx_mac_ra ;
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wire Rx_mac_ra ;
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wire Rx_mac_rd ;
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wire Rx_mac_rd ;
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wire [31:0] Rx_mac_data ;
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wire [31:0] Rx_mac_data ;
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wire [1:0] Rx_mac_BE ;
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wire [1:0] Rx_mac_BE ;
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wire Rx_mac_pa ;
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wire Rx_mac_pa ;
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wire Rx_mac_sop ;
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wire Rx_mac_sop ;
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wire Rx_mac_eop ;
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wire Rx_mac_eop ;
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//user interface
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//user interface
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wire Tx_mac_wa ;
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wire Tx_mac_wa ;
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wire Tx_mac_wr ;
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wire Tx_mac_wr ;
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wire [31:0] Tx_mac_data ;
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wire [31:0] Tx_mac_data ;
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wire [1:0] Tx_mac_BE ;//big endian
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wire [1:0] Tx_mac_BE ;//big endian
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wire Tx_mac_sop ;
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wire Tx_mac_sop ;
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wire Tx_mac_eop ;
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wire Tx_mac_eop ;
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//Phy interface
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//Phy interface
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//Phy interface
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//Phy interface
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wire Gtx_clk ;//used only in GMII mode
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wire Gtx_clk ;//used only in GMII mode
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wire Rx_clk ;
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wire Rx_clk ;
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wire Tx_clk ;//used only in MII mode
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wire Tx_clk ;//used only in MII mode
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wire Tx_er ;
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wire Tx_er ;
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wire Tx_en ;
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wire Tx_en ;
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wire [7:0] Txd ;
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wire [7:0] Txd ;
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wire Rx_er ;
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wire Rx_er ;
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wire Rx_dv ;
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wire Rx_dv ;
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wire [7:0] Rxd ;
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wire [7:0] Rxd ;
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wire Crs ;
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wire Crs ;
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wire Col ;
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wire Col ;
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wire CSB ;
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wire CSB ;
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wire WRB ;
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wire WRB ;
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wire [15:0] CD_in ;
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wire [15:0] CD_in ;
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wire [15:0] CD_out ;
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wire [15:0] CD_out ;
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wire [7:0] CA ;
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wire [7:0] CA ;
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//Phy int host interface
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//Phy int host interface
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wire Line_loop_en ;
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wire Line_loop_en ;
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wire [2:0] Speed ;
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wire [2:0] Speed ;
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//mii
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//mii
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wire Mdio ;// MII Management Data In
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wire Mdio ;// MII Management Data In
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wire Mdc ;// MII Management Data Clock
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wire Mdc ;// MII Management Data Clock
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wire CPU_init_end ;
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wire CPU_init_end ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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|
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initial
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initial
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begin
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begin
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Reset =1;
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Reset =1;
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#20 Reset =0;
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#20 Reset =0;
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end
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end
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always
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always
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begin
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begin
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#4 Clk_125M=0;
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#4 Clk_125M=0;
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#4 Clk_125M=1;
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#4 Clk_125M=1;
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end
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end
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|
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always
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always
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begin
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begin
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#5 Clk_user=0;
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#5 Clk_user=0;
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#5 Clk_user=1;
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#5 Clk_user=1;
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end
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end
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|
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always
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always
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begin
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begin
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#10 Clk_reg=0;
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#10 Clk_reg=0;
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#10 Clk_reg=1;
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#10 Clk_reg=1;
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end
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end
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|
|
|
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initial
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initial
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begin
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begin
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$shm_open("tb_top.shm",,900000000,);
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$shm_open("tb_top.shm",,900000000,);
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$shm_probe("AS");
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$shm_probe("AS");
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end
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end
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MAC_top U_MAC_top(
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MAC_top U_MAC_top(
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//system signals (//system signals ),
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//system signals (//system signals ),
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.Reset (Reset ),
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.Reset (Reset ),
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.Clk_125M (Clk_125M ),
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.Clk_125M (Clk_125M ),
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.Clk_user (Clk_user ),
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.Clk_user (Clk_user ),
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.Clk_reg (Clk_reg ),
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.Clk_reg (Clk_reg ),
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.Speed (Speed ),
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.Speed (Speed ),
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//user interface (//user interface ),
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//user interface (//user interface ),
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.Rx_mac_ra (Rx_mac_ra ),
|
.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_pa (Rx_mac_pa ),
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.Rx_mac_pa (Rx_mac_pa ),
|
.Rx_mac_sop (Rx_mac_sop ),
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.Rx_mac_sop (Rx_mac_sop ),
|
.Rx_mac_eop (Rx_mac_eop ),
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.Rx_mac_eop (Rx_mac_eop ),
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//user interface (//user interface ),
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//user interface (//user interface ),
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.Tx_mac_wa (Tx_mac_wa ),
|
.Tx_mac_wa (Tx_mac_wa ),
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.Tx_mac_wr (Tx_mac_wr ),
|
.Tx_mac_wr (Tx_mac_wr ),
|
.Tx_mac_data (Tx_mac_data ),
|
.Tx_mac_data (Tx_mac_data ),
|
.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_eop (Tx_mac_eop ),
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.Tx_mac_eop (Tx_mac_eop ),
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//Phy interface (//Phy interface ),
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//Phy interface (//Phy interface ),
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//Phy interface (//Phy interface ),
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//Phy interface (//Phy interface ),
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.Gtx_clk (Gtx_clk ),
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.Gtx_clk (Gtx_clk ),
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.Rx_clk (Rx_clk ),
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.Rx_clk (Rx_clk ),
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.Tx_clk (Tx_clk ),
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.Tx_clk (Tx_clk ),
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.Tx_er (Tx_er ),
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.Tx_er (Tx_er ),
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.Tx_en (Tx_en ),
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.Tx_en (Tx_en ),
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.Txd (Txd ),
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.Txd (Txd ),
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.Rx_er (Rx_er ),
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.Rx_er (Rx_er ),
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.Rx_dv (Rx_dv ),
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.Rx_dv (Rx_dv ),
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.Rxd (Rxd ),
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.Rxd (Rxd ),
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.Crs (Crs ),
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.Crs (Crs ),
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.Col (Col ),
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.Col (Col ),
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//host interface
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//host interface
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.CSB (CSB ),
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.CSB (CSB ),
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.WRB (WRB ),
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.WRB (WRB ),
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.CD_in (CD_in ),
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.CD_in (CD_in ),
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.CD_out (CD_out ),
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.CD_out (CD_out ),
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.CA (CA ),
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.CA (CA ),
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//MII interface signals (//MII interface signals ),
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//MII interface signals (//MII interface signals ),
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.Mdio (Mdio ),
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.Mdio (Mdio ),
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.Mdc (Mdc )
|
.Mdc (Mdc )
|
);
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);
|
|
|
Phy_sim U_Phy_sim (
|
Phy_sim U_Phy_sim (
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.Gtx_clk (Gtx_clk ),
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.Gtx_clk (Gtx_clk ),
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.Rx_clk (Rx_clk ),
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.Rx_clk (Rx_clk ),
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.Tx_clk (Tx_clk ),
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.Tx_clk (Tx_clk ),
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.Tx_er (Tx_er ),
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.Tx_er (Tx_er ),
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.Tx_en (Tx_en ),
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.Tx_en (Tx_en ),
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.Txd (Txd ),
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.Txd (Txd ),
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.Rx_er (Rx_er ),
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.Rx_er (Rx_er ),
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.Rx_dv (Rx_dv ),
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.Rx_dv (Rx_dv ),
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.Rxd (Rxd ),
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.Rxd (Rxd ),
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.Crs (Crs ),
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.Crs (Crs ),
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.Col (Col ),
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.Col (Col ),
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.Speed (Speed )
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.Speed (Speed )
|
);
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);
|
|
|
User_int_sim U_User_int_sim(
|
User_int_sim U_User_int_sim(
|
.Reset (Reset ),
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.Reset (Reset ),
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.Clk_user (Clk_user ),
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.Clk_user (Clk_user ),
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.CPU_init_end (CPU_init_end ),
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.CPU_init_end (CPU_init_end ),
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//user inputerface (//user inputerface ),
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//user inputerface (//user inputerface ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_data (Rx_mac_data ),
|
.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_pa (Rx_mac_pa ),
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.Rx_mac_pa (Rx_mac_pa ),
|
.Rx_mac_sop (Rx_mac_sop ),
|
.Rx_mac_sop (Rx_mac_sop ),
|
.Rx_mac_eop (Rx_mac_eop ),
|
.Rx_mac_eop (Rx_mac_eop ),
|
//user inputerface (//user inputerface ),
|
//user inputerface (//user inputerface ),
|
.Tx_mac_wa (Tx_mac_wa ),
|
.Tx_mac_wa (Tx_mac_wa ),
|
.Tx_mac_wr (Tx_mac_wr ),
|
.Tx_mac_wr (Tx_mac_wr ),
|
.Tx_mac_data (Tx_mac_data ),
|
.Tx_mac_data (Tx_mac_data ),
|
.Tx_mac_BE (Tx_mac_BE ),
|
.Tx_mac_BE (Tx_mac_BE ),
|
.Tx_mac_sop (Tx_mac_sop ),
|
.Tx_mac_sop (Tx_mac_sop ),
|
.Tx_mac_eop (Tx_mac_eop )
|
.Tx_mac_eop (Tx_mac_eop )
|
);
|
);
|
|
|
host_sim U_host_sim(
|
host_sim U_host_sim(
|
.Reset (Reset ),
|
.Reset (Reset ),
|
.Clk_reg (Clk_reg ),
|
.Clk_reg (Clk_reg ),
|
.CSB (CSB ),
|
.CSB (CSB ),
|
.WRB (WRB ),
|
.WRB (WRB ),
|
.CD_in (CD_in ),
|
.CD_in (CD_in ),
|
.CD_out (CD_out ),
|
.CD_out (CD_out ),
|
.CPU_init_end (CPU_init_end ),
|
.CPU_init_end (CPU_init_end ),
|
.CA (CA )
|
.CA (CA )
|
|
|
);
|
);
|
endmodule
|
endmodule
|
|
|
