module Reg_int (
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module Reg_int (
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input Reset ,
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input Reset ,
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input Clk_reg ,
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input Clk_reg ,
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input CSB ,
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input CSB ,
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input WRB ,
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input WRB ,
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input [15:0] CD_in ,
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input [15:0] CD_in ,
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output reg [15:0] CD_out ,
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output reg [15:0] CD_out ,
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input [7:0] CA ,
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input [7:0] CA ,
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//Tx host interface
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//Tx host interface
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output [4:0] Tx_Hwmark ,
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output [4:0] Tx_Hwmark ,
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output [4:0] Tx_Lwmark ,
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output [4:0] Tx_Lwmark ,
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output pause_frame_send_en ,
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output pause_frame_send_en ,
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output [15:0] pause_quanta_set ,
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output [15:0] pause_quanta_set ,
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output MAC_tx_add_en ,
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output MAC_tx_add_en ,
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output FullDuplex ,
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output FullDuplex ,
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output [3:0] MaxRetry ,
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output [3:0] MaxRetry ,
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output [5:0] IFGset ,
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output [5:0] IFGset ,
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output [7:0] MAC_tx_add_prom_data ,
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output [7:0] MAC_tx_add_prom_data ,
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output [2:0] MAC_tx_add_prom_add ,
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output [2:0] MAC_tx_add_prom_add ,
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output MAC_tx_add_prom_wr ,
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output MAC_tx_add_prom_wr ,
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output tx_pause_en ,
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output tx_pause_en ,
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output xoff_cpu ,
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output xoff_cpu ,
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output xon_cpu ,
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output xon_cpu ,
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//Rx host interface
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//Rx host interface
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output MAC_rx_add_chk_en ,
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output MAC_rx_add_chk_en ,
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output [7:0] MAC_rx_add_prom_data ,
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output [7:0] MAC_rx_add_prom_data ,
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output [2:0] MAC_rx_add_prom_add ,
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output [2:0] MAC_rx_add_prom_add ,
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output MAC_rx_add_prom_wr ,
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output MAC_rx_add_prom_wr ,
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output broadcast_filter_en ,
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output broadcast_filter_en ,
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output [15:0] broadcast_bucket_depth ,
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output [15:0] broadcast_bucket_depth ,
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output [15:0] broadcast_bucket_interval ,
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output [15:0] broadcast_bucket_interval ,
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output RX_APPEND_CRC ,
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output RX_APPEND_CRC ,
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output [4:0] Rx_Hwmark ,
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output [4:0] Rx_Hwmark ,
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output [4:0] Rx_Lwmark ,
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output [4:0] Rx_Lwmark ,
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output CRC_chk_en ,
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output CRC_chk_en ,
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output [5:0] RX_IFG_SET ,
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output [5:0] RX_IFG_SET ,
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output [15:0] RX_MAX_LENGTH ,// 1518
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output [15:0] RX_MAX_LENGTH ,// 1518
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output [6:0] RX_MIN_LENGTH ,// 64
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output [6:0] RX_MIN_LENGTH ,// 64
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//RMON host interface
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//RMON host interface
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output [5:0] CPU_rd_addr ,
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output [5:0] CPU_rd_addr ,
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output CPU_rd_apply ,
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output CPU_rd_apply ,
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input CPU_rd_grant ,
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input CPU_rd_grant ,
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input [31:0] CPU_rd_dout ,
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input [31:0] CPU_rd_dout ,
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//Phy int host interface
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//Phy int host interface
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output Line_loop_en ,
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output Line_loop_en ,
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output [2:0] Speed ,
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output [2:0] Speed ,
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//MII to CPU
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//MII to CPU
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output [7:0] Divider ,// Divider for the host clock
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output [7:0] Divider ,// Divider for the host clock
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output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
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output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
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output [4:0] Rgad ,// Register Address (within the PHY)
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output [4:0] Rgad ,// Register Address (within the PHY)
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output [4:0] Fiad ,// PHY Address
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output [4:0] Fiad ,// PHY Address
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output NoPre ,// No Preamble (no 32-bit preamble)
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output NoPre ,// No Preamble (no 32-bit preamble)
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output WCtrlData ,// Write Control Data operation
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output WCtrlData ,// Write Control Data operation
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output RStat ,// Read Status operation
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output RStat ,// Read Status operation
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output ScanStat ,// Scan Status operation
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output ScanStat ,// Scan Status operation
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input Busy ,// Busy Signal
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input Busy ,// Busy Signal
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input LinkFail ,// Link Integrity Signal
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input LinkFail ,// Link Integrity Signal
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input Nvalid ,// Invalid Status (qualifier for the valid scan result)
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input Nvalid ,// Invalid Status (qualifier for the valid scan result)
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input [15:0] Prsd ,// Read Status Data (data read from the PHY)
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input [15:0] Prsd ,// Read Status Data (data read from the PHY)
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input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
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input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
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);
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);
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RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h001e,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0019,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0008,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_004(IFGset ,7'd004,16'h001e,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h001e,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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// RegCPUData U_0_032(CPU_rd_dout_h ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_033(Line_loop_en ,7'd034,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_034(Speed ,7'd035,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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always @ (*)
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always @ (posedge Clk_reg or posedge Reset)
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if (Reset)
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CD_out <=0;
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else if (!CSB&&WRB)
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case (CA[7:1])
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case (CA[7:1])
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7'd00: CD_out=Tx_Hwmark ;
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7'd00: CD_out<=Tx_Hwmark ;
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7'd01: CD_out=Tx_Lwmark ;
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7'd01: CD_out<=Tx_Lwmark ;
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7'd02: CD_out=pause_frame_send_en ;
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7'd02: CD_out<=pause_frame_send_en ;
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7'd03: CD_out=pause_quanta_set ;
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7'd03: CD_out<=pause_quanta_set ;
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7'd04: CD_out=IFGset ;
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7'd04: CD_out<=IFGset ;
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7'd05: CD_out=FullDuplex ;
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7'd05: CD_out<=FullDuplex ;
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7'd06: CD_out=MaxRetry ;
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7'd06: CD_out<=MaxRetry ;
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7'd07: CD_out=MAC_tx_add_en ;
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7'd07: CD_out<=MAC_tx_add_en ;
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7'd08: CD_out=MAC_tx_add_prom_data ;
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7'd08: CD_out<=MAC_tx_add_prom_data ;
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7'd09: CD_out=MAC_tx_add_prom_add ;
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7'd09: CD_out<=MAC_tx_add_prom_add ;
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7'd10: CD_out=MAC_tx_add_prom_wr ;
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7'd10: CD_out<=MAC_tx_add_prom_wr ;
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7'd11: CD_out=tx_pause_en ;
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7'd11: CD_out<=tx_pause_en ;
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7'd12: CD_out=xoff_cpu ;
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7'd12: CD_out<=xoff_cpu ;
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7'd13: CD_out=xon_cpu ;
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7'd13: CD_out<=xon_cpu ;
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7'd14: CD_out=MAC_rx_add_chk_en ;
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7'd14: CD_out<=MAC_rx_add_chk_en ;
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7'd15: CD_out=MAC_rx_add_prom_data ;
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7'd15: CD_out<=MAC_rx_add_prom_data ;
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7'd16: CD_out=MAC_rx_add_prom_add ;
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7'd16: CD_out<=MAC_rx_add_prom_add ;
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7'd17: CD_out=MAC_rx_add_prom_wr ;
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7'd17: CD_out<=MAC_rx_add_prom_wr ;
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7'd18: CD_out=broadcast_filter_en ;
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7'd18: CD_out<=broadcast_filter_en ;
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7'd19: CD_out=broadcast_bucket_depth ;
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7'd19: CD_out<=broadcast_bucket_depth ;
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7'd20: CD_out=broadcast_bucket_interval ;
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7'd20: CD_out<=broadcast_bucket_interval ;
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7'd21: CD_out=RX_APPEND_CRC ;
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7'd21: CD_out<=RX_APPEND_CRC ;
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7'd22: CD_out=Rx_Hwmark ;
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7'd22: CD_out<=Rx_Hwmark ;
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7'd23: CD_out=Rx_Lwmark ;
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7'd23: CD_out<=Rx_Lwmark ;
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7'd24: CD_out=CRC_chk_en ;
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7'd24: CD_out<=CRC_chk_en ;
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7'd25: CD_out=RX_IFG_SET ;
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7'd25: CD_out<=RX_IFG_SET ;
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7'd26: CD_out=RX_MAX_LENGTH ;
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7'd26: CD_out<=RX_MAX_LENGTH ;
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7'd27: CD_out=RX_MIN_LENGTH ;
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7'd27: CD_out<=RX_MIN_LENGTH ;
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7'd28: CD_out=CPU_rd_addr ;
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7'd28: CD_out<=CPU_rd_addr ;
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7'd29: CD_out=CPU_rd_apply ;
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7'd29: CD_out<=CPU_rd_apply ;
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7'd30: CD_out=CPU_rd_grant ;
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7'd30: CD_out<=CPU_rd_grant ;
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7'd31: CD_out=CPU_rd_dout[15:0] ;
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7'd31: CD_out<=CPU_rd_dout[15:0] ;
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7'd32: CD_out=CPU_rd_dout[31:16] ;
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7'd32: CD_out<=CPU_rd_dout[31:16] ;
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7'd33: CD_out=Line_loop_en ;
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7'd33: CD_out<=Line_loop_en ;
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7'd34: CD_out=Speed ;
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7'd34: CD_out<=Speed ;
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default: CD_out=0 ;
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default: CD_out<=0 ;
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endcase
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endcase
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else
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CD_out<=0 ;
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endmodule
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endmodule
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|
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module RegCPUData(
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module RegCPUData(
|
RegOut,
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RegOut,
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CA_reg_set,
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CA_reg_set,
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RegInit,
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RegInit,
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|
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Reset,
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Reset,
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Clk,
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Clk,
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CWR_pulse,
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CWR_pulse,
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CCSB,
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CCSB,
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CA_reg,
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CA_reg,
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CD_in_reg
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CD_in_reg
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);
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);
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output[15:0] RegOut;
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output[15:0] RegOut;
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input[6:0] CA_reg_set;
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input[6:0] CA_reg_set;
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input[15:0] RegInit;
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input[15:0] RegInit;
|
//
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//
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input Reset;
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input Reset;
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input Clk;
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input Clk;
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input CWR_pulse;
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input CWR_pulse;
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input CCSB;
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input CCSB;
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input[7:0] CA_reg;
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input[7:0] CA_reg;
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input[15:0] CD_in_reg;
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input[15:0] CD_in_reg;
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//
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//
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reg[15:0] RegOut;
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reg[15:0] RegOut;
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|
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always @(posedge Reset or posedge Clk)
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always @(posedge Reset or posedge Clk)
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if(Reset)
|
if(Reset)
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RegOut <=RegInit;
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RegOut <=RegInit;
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else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])
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else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])
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RegOut <=CD_in_reg;
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RegOut <=CD_in_reg;
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