variable MAC_SOURCE_REPLACE_EN
|
variable MAC_SOURCE_REPLACE_EN
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variable MAC_TARGET_CHECK_EN
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variable MAC_TARGET_CHECK_EN
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variable MAC_BROADCAST_FILTER_EN
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variable MAC_BROADCAST_FILTER_EN
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variable MAC_TX_FF_DEPTH
|
variable MAC_TX_FF_DEPTH
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variable MAC_RX_FF_DEPTH
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variable MAC_RX_FF_DEPTH
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variable header_data
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variable header_data
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|
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source sim/rtl_sim/ncsim_sim/script/run_proc.tcl
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source sim/rtl_sim/ncsim_sim/script/run_proc.tcl
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|
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frame .f1
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frame .f1
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frame .f2
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frame .f2
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text .f1.t1 -width 60 -height 20
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text .f1.t1 -width 60 -height 20
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button .f2.b1 -text "Quit" -width 5 -command {exit}
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button .f2.b1 -text "Quit" -width 5 -command {exit}
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button .f2.b2 -text "Next" -width 5 -command {module_conf}
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button .f2.b2 -text "Next" -width 5 -command {module_conf}
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|
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pack .f1 .f2
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pack .f1 .f2
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pack .f1.t1
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pack .f1.t1
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pack .f2.b1 .f2.b2 -side left
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pack .f2.b1 .f2.b2 -side left
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|
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set strings \
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set strings \
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{Hi guys,
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{Hi guys,
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Thanks for your interest about this tri-speed ethernet MAC controller.
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Thanks for your interest about this tri-speed ethernet MAC controller.
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Since this project was created at 25-Nov-2005,I put almost all my free time
|
Since this project was created at 25-Nov-2005,I put almost all my free time
|
on this project.I am exhausted for this two month's extra work.If you think
|
on this project.I am exhausted for this two month's extra work.If you think
|
this project is useful,let me know that and i will feel much better.
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this project is useful,let me know that and i will feel much better.
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|
|
To increase the flexibility, some optional modules can be removed from
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To increase the flexibility, some optional modules can be removed from
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the design to reduce area.
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the design to reduce area.
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|
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Any problem or bug report please contact me by email:
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Any problem or bug report please contact me by email:
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gaojon@yahoo.com
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gaojon@yahoo.com
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|
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|
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|
|
|
|
|
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jon
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jon
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18-Jan-2006
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18-Jan-2006
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}
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}
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.f1.t1 insert end $strings
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.f1.t1 insert end $strings
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|
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proc module_conf {} {
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proc module_conf {} {
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global MAC_SOURCE_REPLACE_EN
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global MAC_SOURCE_REPLACE_EN
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global MAC_TARGET_CHECK_EN
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global MAC_TARGET_CHECK_EN
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global MAC_BROADCAST_FILTER_EN
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global MAC_BROADCAST_FILTER_EN
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global MAC_TX_FF_DEPTH
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global MAC_TX_FF_DEPTH
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global MAC_RX_FF_DEPTH
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global MAC_RX_FF_DEPTH
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global header_data
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global header_data
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|
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if {[catch {open ./rtl/verilog/header.v r} fileid]} {
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if {[catch {open ./rtl/verilog/header.v r} fileid]} {
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puts "Failed open ./rtl/verilog/header.v file\n"
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puts "Failed open ./rtl/verilog/header.v file\n"
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} else {
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} else {
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gets $fileid line
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gets $fileid line
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if {[lindex $line 0]=="//"} {
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if {[lindex $line 0]=="//"} {
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set line [lreplace $line 0 0]
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set line [lreplace $line 0 0]
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set MAC_SOURCE_REPLACE_EN 0
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set MAC_SOURCE_REPLACE_EN 0
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} else {
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} else {
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set MAC_SOURCE_REPLACE_EN 1
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set MAC_SOURCE_REPLACE_EN 1
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}
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}
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lappend header_data $line
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lappend header_data $line
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gets $fileid line
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gets $fileid line
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if {[lindex $line 0]=="//"} {
|
if {[lindex $line 0]=="//"} {
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set line [lreplace $line 0 0]
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set line [lreplace $line 0 0]
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set MAC_TARGET_CHECK_EN 0
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set MAC_TARGET_CHECK_EN 0
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} else {
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} else {
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set MAC_TARGET_CHECK_EN 1
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set MAC_TARGET_CHECK_EN 1
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}
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}
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lappend header_data $line
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lappend header_data $line
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gets $fileid line
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gets $fileid line
|
if {[lindex $line 0]=="//"} {
|
if {[lindex $line 0]=="//"} {
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set line [lreplace $line 0 0]
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set line [lreplace $line 0 0]
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set MAC_BROADCAST_FILTER_EN 0
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set MAC_BROADCAST_FILTER_EN 0
|
} else {
|
} else {
|
set MAC_BROADCAST_FILTER_EN 1
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set MAC_BROADCAST_FILTER_EN 1
|
}
|
}
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lappend header_data $line
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lappend header_data $line
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gets $fileid line
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gets $fileid line
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set MAC_TX_FF_DEPTH [lindex $line 2]
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set MAC_TX_FF_DEPTH [lindex $line 2]
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lappend header_data $line
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lappend header_data $line
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gets $fileid line
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gets $fileid line
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set MAC_RX_FF_DEPTH [lindex $line 2]
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set MAC_RX_FF_DEPTH [lindex $line 2]
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lappend header_data $line
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lappend header_data $line
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close $fileid
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close $fileid
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}
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}
|
|
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destroy .f1 .f2
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destroy .f1 .f2
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frame .f1
|
frame .f1
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frame .f2
|
frame .f2
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frame .f1.f1
|
frame .f1.f1
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frame .f1.f2
|
frame .f1.f2
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frame .f1.f3
|
frame .f1.f3
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frame .f1.f4
|
frame .f1.f4
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frame .f1.f5
|
frame .f1.f5
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frame .f1.f6
|
frame .f1.f6
|
|
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pack .f1 .f2
|
pack .f1 .f2
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pack .f1.f1 .f1.f2 .f1.f3 .f1.f4 .f1.f5 .f1.f6
|
pack .f1.f1 .f1.f2 .f1.f3 .f1.f4 .f1.f5 .f1.f6
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label .f1.f1.lb -text "enable source MAC replace module" -width 30
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label .f1.f1.lb -text "enable source MAC replace module" -width 30
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checkbutton .f1.f1.cb -variable MAC_SOURCE_REPLACE_EN
|
checkbutton .f1.f1.cb -variable MAC_SOURCE_REPLACE_EN
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label .f1.f2.lb -text "enable target MAC check module " -width 30
|
label .f1.f2.lb -text "enable target MAC check module " -width 30
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checkbutton .f1.f2.cb -variable MAC_TARGET_CHECK_EN
|
checkbutton .f1.f2.cb -variable MAC_TARGET_CHECK_EN
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label .f1.f3.lb -text "enable broadcast packet filter module" -width 30
|
label .f1.f3.lb -text "enable broadcast packet filter module" -width 30
|
checkbutton .f1.f3.cb -variable MAC_BROADCAST_FILTER_EN
|
checkbutton .f1.f3.cb -variable MAC_BROADCAST_FILTER_EN
|
|
|
label .f1.f4.lb -text "MAC_TX_FF_DEPTH" -width 30
|
label .f1.f4.lb -text "MAC_TX_FF_DEPTH" -width 30
|
entry .f1.f4.en -textvariable MAC_TX_FF_DEPTH -width 5
|
entry .f1.f4.en -textvariable MAC_TX_FF_DEPTH -width 5
|
label .f1.f5.lb -text "MAC_RX_FF_DEPTH" -width 30
|
label .f1.f5.lb -text "MAC_RX_FF_DEPTH" -width 30
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entry .f1.f5.en -textvariable MAC_RX_FF_DEPTH -width 5
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entry .f1.f5.en -textvariable MAC_RX_FF_DEPTH -width 5
|
|
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button .f2.b1 -width 10 -text "Save" -command {save_header}
|
button .f2.b1 -width 10 -text "Save" -command {save_header}
|
button .f2.b2 -width 10 -text "Verify" -command {run_sim}
|
button .f2.b2 -width 10 -text "Verify" -command {run_sim}
|
button .f2.b4 -width 10 -text "Exit" -command {exit}
|
button .f2.b4 -width 10 -text "Exit" -command {exit}
|
|
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pack .f1.f1.cb .f1.f1.lb -side right
|
pack .f1.f1.cb .f1.f1.lb -side right
|
pack .f1.f2.cb .f1.f2.lb -side right
|
pack .f1.f2.cb .f1.f2.lb -side right
|
pack .f1.f3.cb .f1.f3.lb -side right
|
pack .f1.f3.cb .f1.f3.lb -side right
|
pack .f1.f4.en .f1.f4.lb -side right
|
pack .f1.f4.en .f1.f4.lb -side right
|
pack .f1.f5.en .f1.f5.lb -side right
|
pack .f1.f5.en .f1.f5.lb -side right
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|
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pack .f2.b1 .f2.b2 .f2.b4 -side left
|
pack .f2.b1 .f2.b2 .f2.b4 -side left
|
|
|
}
|
}
|
|
|
proc save_header {} {
|
proc save_header {} {
|
global MAC_SOURCE_REPLACE_EN
|
global MAC_SOURCE_REPLACE_EN
|
global MAC_TARGET_CHECK_EN
|
global MAC_TARGET_CHECK_EN
|
global MAC_BROADCAST_FILTER_EN
|
global MAC_BROADCAST_FILTER_EN
|
global MAC_TX_FF_DEPTH
|
global MAC_TX_FF_DEPTH
|
global MAC_RX_FF_DEPTH
|
global MAC_RX_FF_DEPTH
|
global header_data
|
global header_data
|
if {[catch {open ./rtl/verilog/header.v w} fileid]} {
|
if {[catch {open ./rtl/verilog/header.v w} fileid]} {
|
puts "Failed open ./rtl/verilog/header.v file\n"
|
puts "Failed open ./rtl/verilog/header.v file\n"
|
} else {
|
} else {
|
set line [lindex $header_data 0]
|
set line [lindex $header_data 0]
|
if {$MAC_SOURCE_REPLACE_EN==0} {
|
if {$MAC_SOURCE_REPLACE_EN==0} {
|
set line [linsert $line 0 "//"]
|
set line [linsert $line 0 "//"]
|
}
|
}
|
puts $fileid $line
|
puts $fileid $line
|
|
|
set line [lindex $header_data 1]
|
set line [lindex $header_data 1]
|
if {$MAC_TARGET_CHECK_EN==0} {
|
if {$MAC_TARGET_CHECK_EN==0} {
|
set line [linsert $line 0 "//"]
|
set line [linsert $line 0 "//"]
|
}
|
}
|
puts $fileid $line
|
puts $fileid $line
|
|
|
set line [lindex $header_data 2]
|
set line [lindex $header_data 2]
|
if {$MAC_BROADCAST_FILTER_EN==0} {
|
if {$MAC_BROADCAST_FILTER_EN==0} {
|
set line [linsert $line 0 "//"]
|
set line [linsert $line 0 "//"]
|
}
|
}
|
puts $fileid $line
|
puts $fileid $line
|
|
|
set line [lindex $header_data 3]
|
set line [lindex $header_data 3]
|
set line [lreplace $line 2 2 $MAC_TX_FF_DEPTH]
|
set line [lreplace $line 2 2 $MAC_TX_FF_DEPTH]
|
puts $fileid $line
|
puts $fileid $line
|
|
|
set line [lindex $header_data 4]
|
set line [lindex $header_data 4]
|
set line [lreplace $line 2 2 $MAC_RX_FF_DEPTH]
|
set line [lreplace $line 2 2 $MAC_RX_FF_DEPTH]
|
puts $fileid $line
|
puts $fileid $line
|
|
|
close $fileid
|
close $fileid
|
}
|
}
|
|
|
}
|
}
|
|
|
proc start_verify {} {
|
proc start_verify {} {
|
cd sim/rtl_sim/ncsim_sim/script
|
cd sim/rtl_sim/ncsim_sim/script
|
vish run.tcl
|
vish run.tcl
|
}
|
}
|
|
|
proc start_syn {} {
|
proc start_syn {} {
|
cd syn
|
cd syn
|
synplify_pro syn.prj
|
synplify_pro syn.prj
|
}
|
}
|
|
|
proc run_sim {} {
|
proc run_sim {} {
|
cd sim/rtl_sim/ncsim_sim/script/
|
cd sim/rtl_sim/ncsim_sim/script/
|
run_proc
|
run_proc
|
|
|
