//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MAC_tx_ctrl.v ////
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//// MAC_tx_ctrl.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
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//// ////
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//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2005/12/16 06:44:17 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.2 2005/12/13 12:15:38 Administrator
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// no message
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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// no message
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//
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//
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module MAC_tx_ctrl (
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module MAC_tx_ctrl (
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Reset ,
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Reset ,
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Clk ,
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Clk ,
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//CRC_gen Interface
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//CRC_gen Interface
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CRC_init ,
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CRC_init ,
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Frame_data ,
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Frame_data ,
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Data_en ,
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Data_en ,
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CRC_rd ,
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CRC_rd ,
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CRC_end ,
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CRC_end ,
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CRC_out ,
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CRC_out ,
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//Ramdon_gen interfac
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//Ramdon_gen interfac
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Random_init ,
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Random_init ,
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RetryCnt ,
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RetryCnt ,
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Random_time_meet ,
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Random_time_meet ,
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//flow control
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//flow control
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pause_apply ,
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pause_apply ,
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pause_quanta_sub ,
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pause_quanta_sub ,
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xoff_gen ,
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xoff_gen ,
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xoff_gen_complete ,
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xoff_gen_complete ,
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xon_gen ,
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xon_gen ,
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xon_gen_complete ,
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xon_gen_complete ,
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//MAC_tx_FF
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//MAC_tx_FF
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Fifo_data ,
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Fifo_data ,
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Fifo_rd ,
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Fifo_rd ,
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Fifo_eop ,
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Fifo_eop ,
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Fifo_da ,
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Fifo_da ,
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Fifo_rd_finish ,
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Fifo_rd_finish ,
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Fifo_rd_retry ,
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Fifo_rd_retry ,
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Fifo_ra ,
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Fifo_ra ,
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Fifo_data_err_empty ,
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Fifo_data_err_empty ,
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Fifo_data_err_full ,
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Fifo_data_err_full ,
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//RMII
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//RMII
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TxD ,
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TxD ,
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TxEn ,
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TxEn ,
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CRS ,
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CRS ,
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//MAC_tx_addr_add
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//MAC_tx_addr_add
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MAC_tx_addr_rd ,
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MAC_tx_addr_rd ,
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MAC_tx_addr_data ,
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MAC_tx_addr_data ,
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MAC_tx_addr_init ,
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MAC_tx_addr_init ,
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//RMON
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//RMON
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Tx_pkt_type_rmon ,
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Tx_pkt_type_rmon ,
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Tx_pkt_length_rmon ,
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Tx_pkt_length_rmon ,
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Tx_apply_rmon ,
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Tx_apply_rmon ,
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Tx_pkt_err_type_rmon,
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Tx_pkt_err_type_rmon,
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//CPU
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//CPU
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pause_frame_send_en ,
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pause_frame_send_en ,
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pause_quanta_set ,
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pause_quanta_set ,
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MAC_tx_add_en ,
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MAC_tx_add_en ,
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FullDuplex ,
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FullDuplex ,
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MaxRetry ,
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MaxRetry ,
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IFGset
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IFGset
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);
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);
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|
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input Reset ;
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input Reset ;
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input Clk ;
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input Clk ;
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//CRC_gen Interface
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//CRC_gen Interface
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output CRC_init ;
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output CRC_init ;
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output[7:0] Frame_data ;
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output [7:0] Frame_data ;
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output Data_en ;
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output Data_en ;
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output CRC_rd ;
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output CRC_rd ;
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input CRC_end ;
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input CRC_end ;
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input[7:0] CRC_out ;
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input [7:0] CRC_out ;
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//Ramdon_gen interface
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//Ramdon_gen interface
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output Random_init ;
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output Random_init ;
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output[3:0] RetryCnt ;
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output [3:0] RetryCnt ;
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input Random_time_meet ;//levle hight indicate random time passed away
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input Random_time_meet ;//levle hight indicate random time passed away
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//flow control
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//flow control
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input pause_apply ;
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input pause_apply ;
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output pause_quanta_sub ;
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output pause_quanta_sub ;
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input xoff_gen ;
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input xoff_gen ;
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output xoff_gen_complete ;
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output xoff_gen_complete ;
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input xon_gen ;
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input xon_gen ;
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output xon_gen_complete ;
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output xon_gen_complete ;
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//MAC_rx_FF
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//MAC_rx_FF
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input[7:0] Fifo_data ;
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input [7:0] Fifo_data ;
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output Fifo_rd ;
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output Fifo_rd ;
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input Fifo_eop ;
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input Fifo_eop ;
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input Fifo_da ;
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input Fifo_da ;
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output Fifo_rd_finish ;
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output Fifo_rd_finish ;
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output Fifo_rd_retry ;
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output Fifo_rd_retry ;
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input Fifo_ra ;
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input Fifo_ra ;
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input Fifo_data_err_empty ;
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input Fifo_data_err_empty ;
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input Fifo_data_err_full ;
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input Fifo_data_err_full ;
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//RMII
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//RMII
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output[7:0] TxD ;
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output [7:0] TxD ;
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output TxEn ;
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output TxEn ;
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input CRS ;
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input CRS ;
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//MAC_tx_addr_add
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//MAC_tx_addr_add
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output MAC_tx_addr_init ;
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output MAC_tx_addr_init ;
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output MAC_tx_addr_rd ;
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output MAC_tx_addr_rd ;
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input[7:0] MAC_tx_addr_data ;
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input [7:0] MAC_tx_addr_data ;
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//RMON
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//RMON
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output[2:0] Tx_pkt_type_rmon ;
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output [2:0] Tx_pkt_type_rmon ;
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output[15:0] Tx_pkt_length_rmon ;
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output [15:0] Tx_pkt_length_rmon ;
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output Tx_apply_rmon ;
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output Tx_apply_rmon ;
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output[2:0] Tx_pkt_err_type_rmon;
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output [2:0] Tx_pkt_err_type_rmon;
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//CPU
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//CPU
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input pause_frame_send_en ;
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input pause_frame_send_en ;
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input[15:0] pause_quanta_set ;
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input [15:0] pause_quanta_set ;
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input MAC_tx_add_en ;
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input MAC_tx_add_en ;
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input FullDuplex ;
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input FullDuplex ;
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input[3:0] MaxRetry ;
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input [3:0] MaxRetry ;
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input[5:0] IFGset ;
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input [5:0] IFGset ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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parameter StateIdle =4'd00;
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parameter StateIdle =4'd00;
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parameter StatePreamble =4'd01;
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parameter StatePreamble =4'd01;
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parameter StateSFD =4'd02;
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parameter StateSFD =4'd02;
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parameter StateData =4'd03;
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parameter StateData =4'd03;
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parameter StatePause =4'd04;
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parameter StatePause =4'd04;
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parameter StatePAD =4'd05;
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parameter StatePAD =4'd05;
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parameter StateFCS =4'd06;
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parameter StateFCS =4'd06;
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parameter StateIFG =4'd07;
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parameter StateIFG =4'd07;
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parameter StateJam =4'd08;
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parameter StateJam =4'd08;
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parameter StateBackOff =4'd09;
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parameter StateBackOff =4'd09;
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parameter StateJamDrop =4'd10;
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parameter StateJamDrop =4'd10;
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parameter StateFFEmptyDrop =4'd11;
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parameter StateFFEmptyDrop =4'd11;
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parameter StateSwitchNext =4'd12;
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parameter StateSwitchNext =4'd12;
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parameter StateDefer =4'd13;
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parameter StateDefer =4'd13;
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parameter StateSendPauseFrame =4'd14;
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parameter StateSendPauseFrame =4'd14;
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|
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reg[3:0] Current_state /*synthesis syn_keep=1 */;
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reg [3:0] Current_state /*synthesis syn_keep=1 */;
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reg[3:0] Next_state;
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reg [3:0] Next_state;
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reg[5:0] IFG_counter;
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reg [5:0] IFG_counter;
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reg[4:0] Preamble_counter;//
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reg [4:0] Preamble_counter;//
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reg[7:0] TxD_tmp ;
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reg [7:0] TxD_tmp ;
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reg TxEn_tmp ;
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reg TxEn_tmp ;
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reg[15:0] Tx_pkt_length_rmon ;
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reg [15:0] Tx_pkt_length_rmon ;
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reg Tx_apply_rmon ;
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reg Tx_apply_rmon ;
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reg[2:0] Tx_pkt_err_type_rmon;
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reg [2:0] Tx_pkt_err_type_rmon;
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reg[3:0] RetryCnt ;
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reg [3:0] RetryCnt ;
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reg Random_init ;
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reg Random_init ;
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reg Fifo_rd_finish ;
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reg Fifo_rd_finish ;
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reg Fifo_rd_retry ;
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reg Fifo_rd_retry ;
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reg[7:0] TxD ;
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reg [7:0] TxD ;
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reg TxEn ;
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reg TxEn ;
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reg CRC_init ;
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reg CRC_init ;
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reg Data_en ;
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reg Data_en ;
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reg CRC_rd ;
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reg CRC_rd ;
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reg Fifo_rd ;
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reg Fifo_rd ;
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reg MAC_tx_addr_rd ;
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reg MAC_tx_addr_rd ;
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reg MAC_header_slot ;
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reg MAC_header_slot ;
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reg MAC_header_slot_tmp ;
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reg MAC_header_slot_tmp ;
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reg[2:0] Tx_pkt_type_rmon ;
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reg [2:0] Tx_pkt_type_rmon ;
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wire Collision ;
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wire Collision ;
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reg MAC_tx_addr_init ;
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reg MAC_tx_addr_init ;
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reg Src_MAC_ptr ;
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reg Src_MAC_ptr ;
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reg[7:0] IPLengthCounter ;//for pad append
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reg [7:0] IPLengthCounter ;//for pad append
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reg[1:0] PADCounter ;
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reg [1:0] PADCounter ;
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reg[7:0] JamCounter ;
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reg [7:0] JamCounter ;
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reg PktDrpEvenPtr ;
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reg PktDrpEvenPtr ;
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reg[7:0] pause_counter ;
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reg [7:0] pause_counter ;
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reg pause_quanta_sub ;
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reg pause_quanta_sub ;
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reg pause_frame_send_en_dl1 ;
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reg pause_frame_send_en_dl1 ;
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reg[15:0] pause_quanta_set_dl1 ;
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reg [15:0] pause_quanta_set_dl1 ;
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reg [4:0] send_pause_frame_counter ;
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reg [4:0] send_pause_frame_counter ;
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reg xoff_gen_reg ;
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reg xon_gen_reg ;
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reg xoff_gen_complete ;
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reg xoff_gen_complete ;
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reg xon_gen_complete ;
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reg xon_gen_complete ;
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//******************************************************************************
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//******************************************************************************
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//boundery signal processing
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//boundery signal processing
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//******************************************************************************
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//******************************************************************************
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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begin
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pause_frame_send_en_dl1 <=0;
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pause_frame_send_en_dl1 <=0;
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pause_quanta_set_dl1 <=0;
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pause_quanta_set_dl1 <=0;
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end
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end
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else
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else
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begin
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begin
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pause_frame_send_en_dl1 <=pause_frame_send_en ;
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pause_frame_send_en_dl1 <=pause_frame_send_en ;
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pause_quanta_set_dl1 <=pause_quanta_set ;
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pause_quanta_set_dl1 <=pause_quanta_set ;
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end
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end
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//******************************************************************************
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//******************************************************************************
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//state machine
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//state machine
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//******************************************************************************
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//******************************************************************************
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assign Collision=TxEn&CRS;
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assign Collision=TxEn&CRS;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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send_pause_frame_counter <=0;
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send_pause_frame_counter <=0;
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else if(Current_state!=StateSendPauseFrame)
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else if(Current_state!=StateSendPauseFrame)
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send_pause_frame_counter <=0;
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send_pause_frame_counter <=0;
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else
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else
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send_pause_frame_counter <=send_pause_frame_counter +1;
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send_pause_frame_counter <=send_pause_frame_counter +1;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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pause_counter <=0;
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pause_counter <=0;
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else if (Current_state!=StatePause)
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else if (Current_state!=StatePause)
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pause_counter <=0;
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pause_counter <=0;
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else
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else
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pause_counter <=pause_counter+1;
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pause_counter <=pause_counter+1;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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IPLengthCounter <=0;
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IPLengthCounter <=0;
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else if (Current_state==StateSwitchNext)
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else if (Current_state==StateSwitchNext)
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IPLengthCounter <=0;
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IPLengthCounter <=0;
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else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StatePAD))
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else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StatePAD))
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IPLengthCounter <=IPLengthCounter+1;
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IPLengthCounter <=IPLengthCounter+1;
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|
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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PADCounter <=0;
|
PADCounter <=0;
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else if (Current_state!=StatePAD)
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else if (Current_state!=StatePAD)
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PADCounter <=0;
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PADCounter <=0;
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else
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else
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PADCounter <=PADCounter+1;
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PADCounter <=PADCounter+1;
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|
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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Current_state <=StateDefer;
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Current_state <=StateDefer;
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else
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else
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Current_state <=Next_state;
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Current_state <=Next_state;
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|
|
always @ (*)
|
always @ (*)
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case (Current_state)
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case (Current_state)
|
StateDefer:
|
StateDefer:
|
if ((FullDuplex)||(!FullDuplex&&!CRS))
|
if ((FullDuplex)||(!FullDuplex&&!CRS))
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Next_state=StateIFG;
|
Next_state=StateIFG;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StateIFG:
|
StateIFG:
|
if (!FullDuplex&&CRS)
|
if (!FullDuplex&&CRS)
|
Next_state=StateDefer;
|
Next_state=StateDefer;
|
else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//È¥µôһЩµ¢¸éµÄʱ¼ä
|
else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//È¥µôһЩµ¢¸éµÄʱ¼ä
|
Next_state=StateIdle;
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Next_state=StateIdle;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StateIdle:
|
StateIdle:
|
if (!FullDuplex&&CRS)
|
if (!FullDuplex&&CRS)
|
Next_state=StateDefer;
|
Next_state=StateDefer;
|
else if (pause_apply)
|
else if (pause_apply)
|
Next_state=StatePause;
|
Next_state=StatePause;
|
else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg)))
|
else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
|
Next_state=StatePreamble;
|
Next_state=StatePreamble;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StatePause:
|
StatePause:
|
if (pause_counter==512/8)
|
if (pause_counter==512/8)
|
Next_state=StateDefer;
|
Next_state=StateDefer;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StatePreamble:
|
StatePreamble:
|
if (!FullDuplex&&Collision)
|
if (!FullDuplex&&Collision)
|
Next_state=StateJam;
|
Next_state=StateJam;
|
else if ((FullDuplex&&Preamble_counter==7)||(!FullDuplex&&!Collision&&Preamble_counter==7))
|
else if ((FullDuplex&&Preamble_counter==7)||(!FullDuplex&&!Collision&&Preamble_counter==7))
|
Next_state=StateSFD;
|
Next_state=StateSFD;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StateSFD:
|
StateSFD:
|
if (!FullDuplex&&Collision)
|
if (!FullDuplex&&Collision)
|
Next_state=StateJam;
|
Next_state=StateJam;
|
else if (pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg))
|
else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
|
Next_state=StateSendPauseFrame;
|
Next_state=StateSendPauseFrame;
|
else
|
else
|
Next_state=StateData;
|
Next_state=StateData;
|
StateSendPauseFrame:
|
StateSendPauseFrame:
|
if (send_pause_frame_counter==19)
|
if (send_pause_frame_counter==19)
|
Next_state=StatePAD;
|
Next_state=StatePAD;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StateData:
|
StateData:
|
if (!FullDuplex&&Collision)
|
if (!FullDuplex&&Collision)
|
Next_state=StateJam;
|
Next_state=StateJam;
|
else if (Fifo_data_err_empty)
|
else if (Fifo_data_err_empty)
|
Next_state=StateFFEmptyDrop;
|
Next_state=StateFFEmptyDrop;
|
else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0
|
else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0
|
Next_state=StateFCS;
|
Next_state=StateFCS;
|
else if (Fifo_eop)
|
else if (Fifo_eop)
|
Next_state=StatePAD;
|
Next_state=StatePAD;
|
else
|
else
|
Next_state=StateData;
|
Next_state=StateData;
|
StatePAD:
|
StatePAD:
|
if (!FullDuplex&&Collision)
|
if (!FullDuplex&&Collision)
|
Next_state=StateJam;
|
Next_state=StateJam;
|
else if (IPLengthCounter>=59)
|
else if (IPLengthCounter>=59)
|
Next_state=StateFCS;
|
Next_state=StateFCS;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StateJam:
|
StateJam:
|
if (RetryCnt<=MaxRetry&&JamCounter==16)
|
if (RetryCnt<=MaxRetry&&JamCounter==16)
|
Next_state=StateBackOff;
|
Next_state=StateBackOff;
|
else if (RetryCnt>MaxRetry)
|
else if (RetryCnt>MaxRetry)
|
Next_state=StateJamDrop;
|
Next_state=StateJamDrop;
|
else
|
else
|
Next_state=Current_state;
|
Next_state=Current_state;
|
StateBackOff:
|
StateBackOff:
|
if (Random_time_meet)
|
if (Random_time_meet)
|
Next_state =StateDefer;
|
Next_state =StateDefer;
|
else
|
else
|
Next_state =Current_state;
|
Next_state =Current_state;
|
StateFCS:
|
StateFCS:
|
if (!FullDuplex&&Collision)
|
if (!FullDuplex&&Collision)
|
Next_state =StateJam;
|
Next_state =StateJam;
|
else if (pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg))
|
else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
|
Next_state =StateDefer;
|
Next_state =StateDefer;
|
else if (CRC_end)
|
else if (CRC_end)
|
Next_state =StateSwitchNext;
|
Next_state =StateSwitchNext;
|
else
|
else
|
Next_state =Current_state;
|
Next_state =Current_state;
|
StateFFEmptyDrop:
|
StateFFEmptyDrop:
|
if (Fifo_eop)
|
if (Fifo_eop)
|
Next_state =StateSwitchNext;
|
Next_state =StateSwitchNext;
|
else
|
else
|
Next_state =Current_state;
|
Next_state =Current_state;
|
StateJamDrop:
|
StateJamDrop:
|
if (Fifo_eop)
|
if (Fifo_eop)
|
Next_state =StateSwitchNext;
|
Next_state =StateSwitchNext;
|
else
|
else
|
Next_state =Current_state;
|
Next_state =Current_state;
|
StateSwitchNext:
|
StateSwitchNext:
|
Next_state =StateDefer;
|
Next_state =StateDefer;
|
default:
|
default:
|
Next_state =StateDefer;
|
Next_state =StateDefer;
|
endcase
|
endcase
|
|
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
JamCounter <=0;
|
JamCounter <=0;
|
else if (Current_state!=StateJam)
|
else if (Current_state!=StateJam)
|
JamCounter <=0;
|
JamCounter <=0;
|
else if (Current_state==StateJam)
|
else if (Current_state==StateJam)
|
JamCounter <=JamCounter+1;
|
JamCounter <=JamCounter+1;
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
RetryCnt <=0;
|
RetryCnt <=0;
|
else if (Current_state==StateSwitchNext)
|
else if (Current_state==StateSwitchNext)
|
RetryCnt <=0;
|
RetryCnt <=0;
|
else if (Current_state==StateJam&&Next_state==StateBackOff)
|
else if (Current_state==StateJam&&Next_state==StateBackOff)
|
RetryCnt <=RetryCnt + 1;
|
RetryCnt <=RetryCnt + 1;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
IFG_counter <=0;
|
IFG_counter <=0;
|
else if (Current_state!=StateIFG)
|
else if (Current_state!=StateIFG)
|
IFG_counter <=0;
|
IFG_counter <=0;
|
else
|
else
|
IFG_counter <=IFG_counter + 1;
|
IFG_counter <=IFG_counter + 1;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Preamble_counter <=0;
|
Preamble_counter <=0;
|
else if (Current_state!=StatePreamble)
|
else if (Current_state!=StatePreamble)
|
Preamble_counter <=0;
|
Preamble_counter <=0;
|
else
|
else
|
Preamble_counter <=Preamble_counter+ 1;
|
Preamble_counter <=Preamble_counter+ 1;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
PktDrpEvenPtr <=0;
|
PktDrpEvenPtr <=0;
|
else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
|
else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
|
PktDrpEvenPtr <=~PktDrpEvenPtr;
|
PktDrpEvenPtr <=~PktDrpEvenPtr;
|
//******************************************************************************
|
//******************************************************************************
|
//generate output signals
|
//generate output signals
|
//******************************************************************************
|
//******************************************************************************
|
//CRC related
|
//CRC related
|
always @(Current_state)
|
always @(Current_state)
|
if (Current_state==StateSFD)
|
if (Current_state==StateSFD)
|
CRC_init =1;
|
CRC_init =1;
|
else
|
else
|
CRC_init =0;
|
CRC_init =0;
|
|
|
assign Frame_data=TxD_tmp;
|
assign Frame_data=TxD_tmp;
|
|
|
always @(Current_state)
|
always @(Current_state)
|
if (Current_state==StateData||Current_state==StatePAD)
|
if (Current_state==StateData||Current_state==StatePAD)
|
Data_en =1;
|
Data_en =1;
|
else
|
else
|
Data_en =0;
|
Data_en =0;
|
|
|
always @(Current_state)
|
always @(Current_state)
|
if (Current_state==StateFCS)
|
if (Current_state==StateFCS)
|
CRC_rd =1;
|
CRC_rd =1;
|
else
|
else
|
CRC_rd =0;
|
CRC_rd =0;
|
|
|
//Ramdon_gen interface
|
//Ramdon_gen interface
|
always @(Current_state or Next_state)
|
always @(Current_state or Next_state)
|
if (Current_state==StateJam&&Next_state==StateBackOff)
|
if (Current_state==StateJam&&Next_state==StateBackOff)
|
Random_init =1;
|
Random_init =1;
|
else
|
else
|
Random_init =0;
|
Random_init =0;
|
|
|
//MAC_rx_FF
|
//MAC_rx_FF
|
//data have one cycle delay after fifo read signals
|
//data have one cycle delay after fifo read signals
|
always @ (*)
|
always @ (*)
|
if (Current_state==StateData ||
|
if (Current_state==StateData ||
|
Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg)) ||
|
Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) ||
|
Current_state==StateJamDrop&&PktDrpEvenPtr||
|
Current_state==StateJamDrop&&PktDrpEvenPtr||
|
Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
|
Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
|
Fifo_rd =1;
|
Fifo_rd =1;
|
else
|
else
|
Fifo_rd =0;
|
Fifo_rd =0;
|
|
|
always @ (Current_state)
|
always @ (Current_state)
|
if (Current_state==StateSwitchNext)
|
if (Current_state==StateSwitchNext)
|
Fifo_rd_finish =1;
|
Fifo_rd_finish =1;
|
else
|
else
|
Fifo_rd_finish =0;
|
Fifo_rd_finish =0;
|
|
|
always @ (Current_state)
|
always @ (Current_state)
|
if (Current_state==StateJam)
|
if (Current_state==StateJam)
|
Fifo_rd_retry =1;
|
Fifo_rd_retry =1;
|
else
|
else
|
Fifo_rd_retry =0;
|
Fifo_rd_retry =0;
|
//RMII
|
//RMII
|
always @(Current_state)
|
always @(Current_state)
|
if (Current_state==StatePreamble||Current_state==StateSFD||
|
if (Current_state==StatePreamble||Current_state==StateSFD||
|
Current_state==StateData||
|
Current_state==StateData||Current_state==StateSendPauseFrame||
|
Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
|
Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
|
TxEn_tmp =1;
|
TxEn_tmp =1;
|
else
|
else
|
TxEn_tmp =0;
|
TxEn_tmp =0;
|
|
|
//gen txd data
|
//gen txd data
|
always @(*)
|
always @(*)
|
case (Current_state)
|
case (Current_state)
|
StatePreamble:
|
StatePreamble:
|
TxD_tmp =8'h55;
|
TxD_tmp =8'h55;
|
StateSFD:
|
StateSFD:
|
TxD_tmp =8'hd5;
|
TxD_tmp =8'hd5;
|
StateData:
|
StateData:
|
if (Src_MAC_ptr&&MAC_tx_add_en)
|
if (Src_MAC_ptr&&MAC_tx_add_en)
|
TxD_tmp =MAC_tx_addr_data;
|
TxD_tmp =MAC_tx_addr_data;
|
else
|
else
|
TxD_tmp =Fifo_data;
|
TxD_tmp =Fifo_data;
|
StateSendPauseFrame:
|
StateSendPauseFrame:
|
if (Src_MAC_ptr)
|
if (Src_MAC_ptr)
|
TxD_tmp =MAC_tx_addr_data;
|
TxD_tmp =MAC_tx_addr_data;
|
else
|
else
|
case (send_pause_frame_counter)
|
case (send_pause_frame_counter)
|
5'd0: TxD_tmp =8'h01;
|
5'd0: TxD_tmp =8'h01;
|
5'd1: TxD_tmp =8'h80;
|
5'd1: TxD_tmp =8'h80;
|
5'd2: TxD_tmp =8'hc2;
|
5'd2: TxD_tmp =8'hc2;
|
5'd3: TxD_tmp =8'h00;
|
5'd3: TxD_tmp =8'h00;
|
5'd4: TxD_tmp =8'h00;
|
5'd4: TxD_tmp =8'h00;
|
5'd5: TxD_tmp =8'h01;
|
5'd5: TxD_tmp =8'h01;
|
5'd12: TxD_tmp =8'h88;//type
|
5'd12: TxD_tmp =8'h88;//type
|
5'd13: TxD_tmp =8'h08;//
|
5'd13: TxD_tmp =8'h08;//
|
5'd14: TxD_tmp =8'h00;//opcode
|
5'd14: TxD_tmp =8'h00;//opcode
|
5'd15: TxD_tmp =8'h01;
|
5'd15: TxD_tmp =8'h01;
|
5'd16: TxD_tmp =pause_quanta_set_dl1[15:8];
|
5'd16: TxD_tmp =pause_quanta_set_dl1[15:8];
|
5'd17: TxD_tmp =pause_quanta_set_dl1[7:0];
|
5'd17: TxD_tmp =pause_quanta_set_dl1[7:0];
|
default:TxD_tmp =0;
|
default:TxD_tmp =0;
|
endcase
|
endcase
|
|
|
StatePAD:
|
StatePAD:
|
TxD_tmp =8'h00;
|
TxD_tmp =8'h00;
|
StateJam:
|
StateJam:
|
TxD_tmp =8'h01; //jam sequence
|
TxD_tmp =8'h01; //jam sequence
|
StateFCS:
|
StateFCS:
|
TxD_tmp =CRC_out;
|
TxD_tmp =CRC_out;
|
default:
|
default:
|
TxD_tmp =2'b0;
|
TxD_tmp =2'b0;
|
endcase
|
endcase
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
TxD <=0;
|
TxD <=0;
|
TxEn <=0;
|
TxEn <=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
TxD <=TxD_tmp;
|
TxD <=TxD_tmp;
|
TxEn <=TxEn_tmp;
|
TxEn <=TxEn_tmp;
|
end
|
end
|
//RMON
|
//RMON
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Tx_pkt_length_rmon <=0;
|
Tx_pkt_length_rmon <=0;
|
else if (Current_state==StateSFD)
|
else if (Current_state==StateSFD)
|
Tx_pkt_length_rmon <=0;
|
Tx_pkt_length_rmon <=0;
|
else if (Current_state==StateData)
|
else if (Current_state==StateData)
|
Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;
|
Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Tx_apply_rmon <=0;
|
Tx_apply_rmon <=0;
|
else if ((Fifo_eop&&Current_state==StateJamDrop)||
|
else if ((Fifo_eop&&Current_state==StateJamDrop)||
|
(Fifo_eop&&Current_state==StateFFEmptyDrop)||
|
(Fifo_eop&&Current_state==StateFFEmptyDrop)||
|
CRC_end)
|
CRC_end)
|
Tx_apply_rmon <=1;
|
Tx_apply_rmon <=1;
|
else
|
else
|
Tx_apply_rmon <=0;
|
Tx_apply_rmon <=0;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Tx_pkt_err_type_rmon <=0;
|
Tx_pkt_err_type_rmon <=0;
|
else if(Fifo_eop&&Current_state==StateJamDrop)
|
else if(Fifo_eop&&Current_state==StateJamDrop)
|
Tx_pkt_err_type_rmon <=3'b001;//
|
Tx_pkt_err_type_rmon <=3'b001;//
|
else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
|
else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
|
Tx_pkt_err_type_rmon <=3'b010;//underflow
|
Tx_pkt_err_type_rmon <=3'b010;//underflow
|
else if(Fifo_eop&&Fifo_data_err_full)
|
else if(Fifo_eop&&Fifo_data_err_full)
|
Tx_pkt_err_type_rmon <=3'b011;//overflow
|
Tx_pkt_err_type_rmon <=3'b011;//overflow
|
else if(CRC_end)
|
else if(CRC_end)
|
Tx_pkt_err_type_rmon <=3'b100;
|
Tx_pkt_err_type_rmon <=3'b100;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
MAC_header_slot_tmp <=0;
|
MAC_header_slot_tmp <=0;
|
else if(Current_state==StateSFD&&Next_state==StateData)
|
else if(Current_state==StateSFD&&Next_state==StateData)
|
MAC_header_slot_tmp <=0;
|
MAC_header_slot_tmp <=0;
|
else
|
else
|
MAC_header_slot_tmp <=0;
|
MAC_header_slot_tmp <=0;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
MAC_header_slot <=0;
|
MAC_header_slot <=0;
|
else
|
else
|
MAC_header_slot <=MAC_header_slot_tmp;
|
MAC_header_slot <=MAC_header_slot_tmp;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Tx_pkt_type_rmon <=0;
|
Tx_pkt_type_rmon <=0;
|
else if (Current_state==StateSendPauseFrame)
|
else if (Current_state==StateSendPauseFrame)
|
Tx_pkt_type_rmon <=3'b100;
|
Tx_pkt_type_rmon <=3'b100;
|
else if(MAC_header_slot)
|
else if(MAC_header_slot)
|
Tx_pkt_type_rmon <={1'b0,TxD_tmp};
|
Tx_pkt_type_rmon <={1'b0,TxD_tmp};
|
|
|
|
|
always @(Tx_pkt_length_rmon)
|
always @(Tx_pkt_length_rmon)
|
if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
|
if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
|
Src_MAC_ptr =1;
|
Src_MAC_ptr =1;
|
else
|
else
|
Src_MAC_ptr =0;
|
Src_MAC_ptr =0;
|
|
|
//MAC_tx_addr_add
|
//MAC_tx_addr_add
|
always @ (Tx_pkt_length_rmon or Fifo_rd or Src_MAC_ptr)
|
always @ (posedge Clk or posedge Reset)
|
if (Src_MAC_ptr&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
|
if (Reset)
|
MAC_tx_addr_rd =1;
|
MAC_tx_addr_rd <=0;
|
|
else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
|
|
MAC_tx_addr_rd <=1;
|
else
|
else
|
MAC_tx_addr_rd =0;
|
MAC_tx_addr_rd <=0;
|
|
|
always @ (Tx_pkt_length_rmon or Fifo_rd)
|
always @ (Tx_pkt_length_rmon or Fifo_rd)
|
if ((Tx_pkt_length_rmon==5)&&Fifo_rd)
|
if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
|
MAC_tx_addr_init=1;
|
MAC_tx_addr_init=1;
|
else
|
else
|
MAC_tx_addr_init=0;
|
MAC_tx_addr_init=0;
|
|
|
//flow control
|
//flow control
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
pause_quanta_sub <=0;
|
pause_quanta_sub <=0;
|
else if(pause_counter==512/8)
|
else if(pause_counter==512/8)
|
pause_quanta_sub <=1;
|
pause_quanta_sub <=1;
|
else
|
else
|
pause_quanta_sub <=0;
|
pause_quanta_sub <=0;
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
|
xoff_gen_reg <=0;
|
|
xon_gen_reg <=0;
|
|
end
|
|
else if (Current_state==StateDefer)
|
|
begin
|
|
xoff_gen_reg <=xoff_gen;
|
|
xon_gen_reg <=xon_gen;
|
|
end
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
|
if (Reset)
|
|
xoff_gen_complete <=0;
|
xoff_gen_complete <=0;
|
else if(Current_state==StateDefer&&xoff_gen_reg)
|
else if(Current_state==StateDefer&&xoff_gen)
|
xoff_gen_complete <=1;
|
xoff_gen_complete <=1;
|
else
|
else
|
xoff_gen_complete <=0;
|
xoff_gen_complete <=0;
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
if (Reset)
|
if (Reset)
|
xon_gen_complete <=0;
|
xon_gen_complete <=0;
|
else if(Current_state==StateDefer&&xon_gen_reg)
|
else if(Current_state==StateDefer&&xon_gen)
|
xon_gen_complete <=1;
|
xon_gen_complete <=1;
|
else
|
else
|
xon_gen_complete <=0;
|
xon_gen_complete <=0;
|
|
|
endmodule
|
endmodule
|
|
|
