//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// RMON_addr_gen.v ////
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//// RMON_addr_gen.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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//
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module RMON_addr_gen(
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module RMON_addr_gen(
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Clk ,
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Clk ,
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Reset ,
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Reset ,
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//RMON
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//RMON
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Pkt_type_rmon ,
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Pkt_type_rmon ,
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Pkt_length_rmon ,
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Pkt_length_rmon ,
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Apply_rmon ,//pluse signal looks like eop
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Apply_rmon ,//pluse signal looks like eop
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Pkt_err_type_rmon ,
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Pkt_err_type_rmon ,
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//
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//
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Reg_apply ,
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Reg_apply ,
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Reg_addr ,
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Reg_addr ,
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Reg_data ,
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Reg_data ,
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Reg_next ,
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Reg_next ,
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//CPU
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//CPU
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Reg_drop_apply
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Reg_drop_apply
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);
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);
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input Clk ;
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input Clk ;
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input Reset ;
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input Reset ;
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//RMON
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//RMON
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input[2:0] Pkt_type_rmon ;
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input[2:0] Pkt_type_rmon ;
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input[15:0] Pkt_length_rmon ;
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input[15:0] Pkt_length_rmon ;
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input Apply_rmon ;//pluse signal looks like eop
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input Apply_rmon ;//pluse signal looks like eop
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input[2:0] Pkt_err_type_rmon ;
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input[2:0] Pkt_err_type_rmon ;
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//RMON_ctrl
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//RMON_ctrl
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output Reg_apply ;
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output Reg_apply ;
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output[4:0] Reg_addr ;
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output[4:0] Reg_addr ;
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output[15:0] Reg_data ;
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output[15:0] Reg_data ;
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input Reg_next ;
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input Reg_next ;
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//CPU
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//CPU
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output Reg_drop_apply ;
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output Reg_drop_apply ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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parameter StateIdle =5'b00001;
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parameter StateIdle =5'b00001;
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parameter StatePktLength =5'b00010;
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parameter StatePktLength =5'b00010;
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parameter StatePktNumber =5'b00100;
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parameter StatePktNumber =5'b00100;
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parameter StatePktType =5'b01000;
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parameter StatePktType =5'b01000;
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parameter StatePktRange =5'b10000;
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parameter StatePktRange =5'b10000;
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reg[4:0] CurrentState;
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reg[4:0] CurrentState;
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reg[4:0] NextState;
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reg[4:0] NextState;
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reg[2:0] PktTypeReg ;
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reg[2:0] PktTypeReg ;
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reg[15:0] PktLengthReg ;
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reg[15:0] PktLengthReg ;
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reg[2:0] PktErrTypeReg ;
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reg[2:0] PktErrTypeReg ;
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reg Reg_apply ;
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reg Reg_apply ;
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reg[4:0] Reg_addr ;
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reg[4:0] Reg_addr ;
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reg[15:0] Reg_data ;
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reg[15:0] Reg_data ;
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reg Reg_drop_apply ;
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reg Reg_drop_apply ;
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//******************************************************************************
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//******************************************************************************
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//register boundery signals
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//register boundery signals
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//******************************************************************************
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//******************************************************************************
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reg Apply_rmon_dl1;
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reg Apply_rmon_dl1;
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reg Apply_rmon_dl2;
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reg Apply_rmon_dl2;
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reg Apply_rmon_pulse;
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reg Apply_rmon_pulse;
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reg[2:0] Pkt_type_rmon_dl1 ;
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reg[2:0] Pkt_type_rmon_dl1 ;
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reg[15:0] Pkt_length_rmon_dl1 ;
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reg[15:0] Pkt_length_rmon_dl1 ;
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reg[2:0] Pkt_err_type_rmon_dl1 ;
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reg[2:0] Pkt_err_type_rmon_dl1 ;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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begin
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Pkt_type_rmon_dl1 <=0;
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Pkt_type_rmon_dl1 <=0;
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Pkt_length_rmon_dl1 <=0;
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Pkt_length_rmon_dl1 <=0;
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Pkt_err_type_rmon_dl1 <=0;
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Pkt_err_type_rmon_dl1 <=0;
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end
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end
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else
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else
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begin
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begin
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Pkt_type_rmon_dl1 <=Pkt_type_rmon ;
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Pkt_type_rmon_dl1 <=Pkt_type_rmon ;
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Pkt_length_rmon_dl1 <=Pkt_length_rmon ;
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Pkt_length_rmon_dl1 <=Pkt_length_rmon ;
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Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ;
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Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ;
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end
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end
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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begin
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Apply_rmon_dl1 <=0;
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Apply_rmon_dl1 <=0;
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Apply_rmon_dl2 <=0;
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Apply_rmon_dl2 <=0;
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end
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end
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else
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else
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begin
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begin
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Apply_rmon_dl1 <=Apply_rmon;
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Apply_rmon_dl1 <=Apply_rmon;
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Apply_rmon_dl2 <=Apply_rmon_dl1;
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Apply_rmon_dl2 <=Apply_rmon_dl1;
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end
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end
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always @(Apply_rmon_dl1 or Apply_rmon_dl2)
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always @(Apply_rmon_dl1 or Apply_rmon_dl2)
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if (Apply_rmon_dl1&!Apply_rmon_dl2)
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if (Apply_rmon_dl1&!Apply_rmon_dl2)
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Apply_rmon_pulse =1;
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Apply_rmon_pulse =1;
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else
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else
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Apply_rmon_pulse =0;
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Apply_rmon_pulse =0;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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begin
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PktTypeReg <=0;
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PktTypeReg <=0;
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PktLengthReg <=0;
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PktLengthReg <=0;
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PktErrTypeReg <=0;
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PktErrTypeReg <=0;
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end
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end
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else if (Apply_rmon_pulse&&CurrentState==StateIdle)
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else if (Apply_rmon_pulse&&CurrentState==StateIdle)
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begin
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begin
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PktTypeReg <=Pkt_type_rmon_dl1 ;
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PktTypeReg <=Pkt_type_rmon_dl1 ;
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PktLengthReg <=Pkt_length_rmon_dl1 ;
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PktLengthReg <=Pkt_length_rmon_dl1 ;
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PktErrTypeReg <=Pkt_err_type_rmon_dl1 ;
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PktErrTypeReg <=Pkt_err_type_rmon_dl1 ;
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end
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end
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//******************************************************************************
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//******************************************************************************
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//State Machine
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//State Machine
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//******************************************************************************
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//******************************************************************************
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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CurrentState <=StateIdle;
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CurrentState <=StateIdle;
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else
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else
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CurrentState <=NextState;
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CurrentState <=NextState;
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always @(CurrentState or Apply_rmon_pulse or Reg_next)
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always @(CurrentState or Apply_rmon_pulse or Reg_next)
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case (CurrentState)
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case (CurrentState)
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StateIdle:
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StateIdle:
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if (Apply_rmon_pulse)
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if (Apply_rmon_pulse)
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NextState =StatePktLength;
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NextState =StatePktLength;
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else
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else
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NextState =StateIdle;
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NextState =StateIdle;
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StatePktLength:
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StatePktLength:
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if (Reg_next)
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if (Reg_next)
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NextState =StatePktNumber;
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NextState =StatePktNumber;
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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StatePktNumber:
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StatePktNumber:
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if (Reg_next)
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if (Reg_next)
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NextState =StatePktType;
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NextState =StatePktType;
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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StatePktType:
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StatePktType:
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if (Reg_next)
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if (Reg_next)
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NextState =StatePktRange;
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NextState =StatePktRange;
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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StatePktRange:
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StatePktRange:
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if (Reg_next)
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if (Reg_next)
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NextState =StateIdle;
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NextState =StateIdle;
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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default:
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default:
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NextState =StateIdle;
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NextState =StateIdle;
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endcase
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endcase
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//******************************************************************************
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//******************************************************************************
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//gen output signals
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//gen output signals
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//******************************************************************************
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//******************************************************************************
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//Reg_apply
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//Reg_apply
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always @ (CurrentState)
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always @ (CurrentState)
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if (CurrentState==StatePktLength||CurrentState==StatePktNumber||
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if (CurrentState==StatePktLength||CurrentState==StatePktNumber||
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CurrentState==StatePktType||CurrentState==StatePktRange)
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CurrentState==StatePktType||CurrentState==StatePktRange)
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Reg_apply =1;
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Reg_apply =1;
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else
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else
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Reg_apply =0;
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Reg_apply =0;
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//Reg_addr
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//Reg_addr
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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Reg_addr <=0;
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Reg_addr <=0;
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else case (CurrentState)
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else case (CurrentState)
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StatePktLength:
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StatePktLength:
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Reg_addr <=5'd00;
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Reg_addr <=5'd00;
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StatePktNumber:
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StatePktNumber:
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Reg_addr <=5'd01;
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Reg_addr <=5'd01;
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StatePktType:
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StatePktType:
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case(PktTypeReg)
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case(PktTypeReg)
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3'b011:
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3'b011:
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Reg_addr <=5'd02; //broadcast
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Reg_addr <=5'd02; //broadcast
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3'b001:
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3'b001:
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Reg_addr <=5'd03; //multicast
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Reg_addr <=5'd03; //multicast
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3'b100:
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3'b100:
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Reg_addr <=5'd16; //pause frame
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Reg_addr <=5'd16; //pause frame
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default:
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default:
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Reg_addr <=5'd04; //unicast
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Reg_addr <=5'd04; //unicast
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endcase
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endcase
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StatePktRange:
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StatePktRange:
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case(PktErrTypeReg)
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case(PktErrTypeReg)
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3'b001:
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3'b001:
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Reg_addr <=5'd05;
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Reg_addr <=5'd05;
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3'b010:
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3'b010:
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Reg_addr <=5'd06;
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Reg_addr <=5'd06;
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3'b011:
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3'b011:
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Reg_addr <=5'd07;
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Reg_addr <=5'd07;
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3'b100:
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3'b100:
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if (PktLengthReg<64)
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if (PktLengthReg<64)
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Reg_addr <=5'd08;
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Reg_addr <=5'd08;
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else if (PktLengthReg==64)
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else if (PktLengthReg==64)
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Reg_addr <=5'd09;
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Reg_addr <=5'd09;
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else if (PktLengthReg<128)
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else if (PktLengthReg<128)
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Reg_addr <=5'd10;
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Reg_addr <=5'd10;
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else if (PktLengthReg<256)
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else if (PktLengthReg<256)
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Reg_addr <=5'd11;
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Reg_addr <=5'd11;
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else if (PktLengthReg<512)
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else if (PktLengthReg<512)
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Reg_addr <=5'd12;
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Reg_addr <=5'd12;
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else if (PktLengthReg<1024)
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else if (PktLengthReg<1024)
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Reg_addr <=5'd13;
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Reg_addr <=5'd13;
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else if (PktLengthReg<1519)
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else if (PktLengthReg<1519)
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Reg_addr <=5'd14;
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Reg_addr <=5'd14;
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else
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else
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Reg_addr <=5'd15;
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Reg_addr <=5'd15;
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default:
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default:
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Reg_addr <=5'd05;
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Reg_addr <=5'd05;
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endcase
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endcase
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default:
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default:
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Reg_addr <=5'd05;
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Reg_addr <=5'd05;
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endcase
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endcase
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//Reg_data
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//Reg_data
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always @ (CurrentState or PktLengthReg)
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always @ (CurrentState or PktLengthReg)
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case (CurrentState)
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case (CurrentState)
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StatePktLength:
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StatePktLength:
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Reg_data =PktLengthReg;
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Reg_data =PktLengthReg;
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StatePktNumber:
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StatePktNumber:
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Reg_data =1;
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Reg_data =1;
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StatePktType:
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StatePktType:
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Reg_data =1;
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Reg_data =1;
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StatePktRange:
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StatePktRange:
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Reg_data =1;
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Reg_data =1;
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default:
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default:
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Reg_data =0;
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Reg_data =0;
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endcase
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endcase
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//Reg_drop_apply
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//Reg_drop_apply
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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Reg_drop_apply <=0;
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Reg_drop_apply <=0;
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else if (CurrentState!=StateIdle&&Apply_rmon_pulse)
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else if (CurrentState!=StateIdle&&Apply_rmon_pulse)
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Reg_drop_apply <=1;
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Reg_drop_apply <=1;
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else
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else
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Reg_drop_apply <=0;
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Reg_drop_apply <=0;
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endmodule
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endmodule
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