//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// RMON_CTRL.v ////
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//// RMON_CTRL.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2005/12/16 06:44:19 Administrator
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// Revision 1.2 2005/12/16 06:44:19 Administrator
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// replaced tab with space.
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// replaced tab with space.
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// passed 9.6k length frame test.
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// passed 9.6k length frame test.
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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// no message
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//
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//
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module RMON_CTRL (
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module RMON_CTRL (
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Clk ,
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Clk ,
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Reset ,
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Reset ,
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//RMON_CTRL
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//RMON_CTRL
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Reg_apply_0 ,
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Reg_apply_0 ,
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Reg_addr_0 ,
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Reg_addr_0 ,
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Reg_data_0 ,
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Reg_data_0 ,
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Reg_next_0 ,
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Reg_next_0 ,
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Reg_apply_1 ,
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Reg_apply_1 ,
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Reg_addr_1 ,
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Reg_addr_1 ,
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Reg_data_1 ,
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Reg_data_1 ,
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Reg_next_1 ,
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Reg_next_1 ,
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//dual-port ram
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//dual-port ram
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Addra ,
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Addra ,
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Dina ,
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Dina ,
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Douta ,
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Douta ,
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Wea ,
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Wea ,
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//CPU
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//CPU
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CPU_rd_addr ,
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CPU_rd_addr ,
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CPU_rd_apply ,
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CPU_rd_apply ,
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CPU_rd_grant ,
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CPU_rd_grant ,
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CPU_rd_dout
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CPU_rd_dout
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);
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);
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input Clk ;
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input Clk ;
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input Reset ;
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input Reset ;
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//RMON_CTRL
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//RMON_CTRL
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input Reg_apply_0 ;
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input Reg_apply_0 ;
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input [4:0] Reg_addr_0 ;
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input [4:0] Reg_addr_0 ;
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input [15:0] Reg_data_0 ;
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input [15:0] Reg_data_0 ;
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output Reg_next_0 ;
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output Reg_next_0 ;
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input Reg_apply_1 ;
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input Reg_apply_1 ;
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input [4:0] Reg_addr_1 ;
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input [4:0] Reg_addr_1 ;
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input [15:0] Reg_data_1 ;
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input [15:0] Reg_data_1 ;
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output Reg_next_1 ;
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output Reg_next_1 ;
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//dual-port ram
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//dual-port ram
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//port-a for Rmon
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//port-a for Rmon
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output [5:0] Addra ;
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output [5:0] Addra ;
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output [31:0] Dina ;
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output [31:0] Dina ;
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input [31:0] Douta ;
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input [31:0] Douta ;
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output Wea ;
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output Wea ;
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//CPU
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//CPU
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input [5:0] CPU_rd_addr ;
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input [5:0] CPU_rd_addr ;
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input CPU_rd_apply ;
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input CPU_rd_apply ;
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output CPU_rd_grant ;
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output CPU_rd_grant ;
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output [31:0] CPU_rd_dout ;
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output [31:0] CPU_rd_dout ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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parameter StateCPU =5'd00;
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parameter StateCPU =5'd00;
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parameter StateMAC0 =5'd01;
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parameter StateMAC0 =5'd01;
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parameter StateMAC1 =5'd02;
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parameter StateMAC1 =5'd02;
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reg [4:0] CurrentState;
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reg [4:0] CurrentState;
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reg [4:0] NextState;
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reg [4:0] NextState;
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reg [4:0] CurrentState_reg;
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reg [4:0] CurrentState_reg;
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reg [4:0] StepCounter;
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reg [4:0] StepCounter;
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reg [31:0] DoutaReg;
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reg [31:0] DoutaReg;
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reg [5:0] Addra ;
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reg [5:0] Addra ;
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reg [31:0] Dina;
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reg [31:0] Dina;
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reg Reg_next_0 ;
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reg Reg_next_0 ;
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reg Reg_next_1 ;
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reg Reg_next_1 ;
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reg Write;
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reg Write;
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reg Read;
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reg Read;
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reg Pipeline;
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reg Pipeline;
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reg [31:0] CPU_rd_dout ;
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reg [31:0] CPU_rd_dout ;
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reg CPU_rd_apply_reg ;
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reg CPU_rd_apply_reg ;
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//******************************************************************************
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//******************************************************************************
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//State Machine
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//State Machine
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//******************************************************************************
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//******************************************************************************
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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CurrentState <=StateMAC0;
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CurrentState <=StateMAC0;
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else
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else
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CurrentState <=NextState;
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CurrentState <=NextState;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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CurrentState_reg <=StateMAC0;
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CurrentState_reg <=StateMAC0;
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else if(CurrentState!=StateCPU)
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else if(CurrentState!=StateCPU)
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CurrentState_reg <=CurrentState;
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CurrentState_reg <=CurrentState;
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always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
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always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
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or Reg_apply_1
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or Reg_apply_1
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or StepCounter
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or StepCounter
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)
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)
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case(CurrentState)
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case(CurrentState)
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StateMAC0:
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StateMAC0:
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if(!Reg_apply_0&&CPU_rd_apply_reg)
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if(!Reg_apply_0&&CPU_rd_apply_reg)
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NextState =StateCPU;
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NextState =StateCPU;
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else if(!Reg_apply_0)
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else if(!Reg_apply_0)
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NextState =StateMAC1;
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NextState =StateMAC1;
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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StateMAC1:
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StateMAC1:
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if(!Reg_apply_1&&CPU_rd_apply_reg)
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if(!Reg_apply_1&&CPU_rd_apply_reg)
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NextState =StateCPU;
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NextState =StateCPU;
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else if(!Reg_apply_1)
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else if(!Reg_apply_1)
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NextState =StateMAC0;
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NextState =StateMAC0;
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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StateCPU:
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StateCPU:
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if (StepCounter==3)
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if (StepCounter==3)
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case (CurrentState_reg)
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case (CurrentState_reg)
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StateMAC0 :NextState =StateMAC0 ;
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StateMAC0 :NextState =StateMAC0 ;
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StateMAC1 :NextState =StateMAC1 ;
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StateMAC1 :NextState =StateMAC1 ;
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default :NextState =StateMAC0;
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default :NextState =StateMAC0;
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endcase
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endcase
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else
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else
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NextState =CurrentState;
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NextState =CurrentState;
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default:
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default:
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NextState =StateMAC0;
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NextState =StateMAC0;
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endcase
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endcase
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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StepCounter <=0;
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StepCounter <=0;
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else if(NextState!=CurrentState)
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else if(NextState!=CurrentState)
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StepCounter <=0;
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StepCounter <=0;
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else if (StepCounter!=4'hf)
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else if (StepCounter!=4'hf)
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StepCounter <=StepCounter + 1;
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StepCounter <=StepCounter + 1;
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//******************************************************************************
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//******************************************************************************
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//temp signals
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//temp signals
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//******************************************************************************
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//******************************************************************************
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always @(StepCounter)
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always @(StepCounter)
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if( StepCounter==1||StepCounter==4||
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if( StepCounter==1||StepCounter==4||
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StepCounter==7||StepCounter==10)
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StepCounter==7||StepCounter==10)
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Read =1;
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Read =1;
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else
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else
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Read =0;
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Read =0;
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always @(StepCounter or CurrentState)
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always @(StepCounter or CurrentState)
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if( StepCounter==2||StepCounter==5||
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if( StepCounter==2||StepCounter==5||
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StepCounter==8||StepCounter==11)
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StepCounter==8||StepCounter==11)
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Pipeline =1;
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Pipeline =1;
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else
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else
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Pipeline =0;
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Pipeline =0;
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always @(StepCounter or CurrentState)
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always @(StepCounter or CurrentState)
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if( StepCounter==3||StepCounter==6||
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if( StepCounter==3||StepCounter==6||
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StepCounter==9||StepCounter==12)
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StepCounter==9||StepCounter==12)
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Write =1;
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Write =1;
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else
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else
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Write =0;
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Write =0;
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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DoutaReg <=0;
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DoutaReg <=0;
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else if (Read)
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else if (Read)
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DoutaReg <=Douta;
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DoutaReg <=Douta;
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//******************************************************************************
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//******************************************************************************
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//gen output signals
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//gen output signals
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//******************************************************************************
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//******************************************************************************
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//Addra
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//Addra
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always @(*)
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always @(*)
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case(CurrentState)
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case(CurrentState)
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StateMAC0 : Addra={1'd0 ,Reg_addr_0 };
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StateMAC0 : Addra={1'd0 ,Reg_addr_0 };
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StateMAC1 : Addra={1'd1 ,Reg_addr_1 };
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StateMAC1 : Addra={1'd1 ,Reg_addr_1 };
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StateCPU: Addra=CPU_rd_addr;
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StateCPU: Addra=CPU_rd_addr;
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default: Addra=0;
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default: Addra=0;
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endcase
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endcase
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//Dina
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//Dina
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always @(posedge Clk or posedge Reset)
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always @(posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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Dina <=0;
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Dina <=0;
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else
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else
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case(CurrentState)
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case(CurrentState)
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StateMAC0 : Dina<=Douta+Reg_data_0 ;
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StateMAC0 : Dina<=Douta+Reg_data_0 ;
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StateMAC1 : Dina<=Douta+Reg_data_1 ;
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StateMAC1 : Dina<=Douta+Reg_data_1 ;
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StateCPU: Dina<=0;
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StateCPU: Dina<=0;
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default: Dina<=0;
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default: Dina<=0;
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endcase
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endcase
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assign Wea =Write;
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assign Wea =Write;
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//Reg_next
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//Reg_next
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always @(CurrentState or Pipeline)
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always @(CurrentState or Pipeline)
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if(CurrentState==StateMAC0)
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if(CurrentState==StateMAC0)
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Reg_next_0 =Pipeline;
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Reg_next_0 =Pipeline;
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else
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else
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Reg_next_0 =0;
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Reg_next_0 =0;
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always @(CurrentState or Pipeline)
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always @(CurrentState or Pipeline)
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if(CurrentState==StateMAC1)
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if(CurrentState==StateMAC1)
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Reg_next_1 =Pipeline;
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Reg_next_1 =Pipeline;
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else
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else
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Reg_next_1 =0;
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Reg_next_1 =0;
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//CPU_rd_grant
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//CPU_rd_grant
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reg CPU_rd_apply_dl1;
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reg CPU_rd_apply_dl1;
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reg CPU_rd_apply_dl2;
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reg CPU_rd_apply_dl2;
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//rising edge
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//rising edge
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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begin
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CPU_rd_apply_dl1 <=0;
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CPU_rd_apply_dl1 <=0;
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CPU_rd_apply_dl2 <=0;
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CPU_rd_apply_dl2 <=0;
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end
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end
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else
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else
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begin
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begin
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CPU_rd_apply_dl1 <=CPU_rd_apply;
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CPU_rd_apply_dl1 <=CPU_rd_apply;
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CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;
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CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;
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end
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end
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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CPU_rd_apply_reg <=0;
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CPU_rd_apply_reg <=0;
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else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
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else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
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CPU_rd_apply_reg <=1;
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CPU_rd_apply_reg <=1;
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else if (CurrentState==StateCPU&&Write)
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else if (CurrentState==StateCPU&&Write)
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CPU_rd_apply_reg <=0;
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CPU_rd_apply_reg <=0;
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assign CPU_rd_grant =!CPU_rd_apply_reg;
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assign CPU_rd_grant =!CPU_rd_apply_reg;
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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CPU_rd_dout <=0;
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CPU_rd_dout <=0;
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else if (Pipeline&&CurrentState==StateCPU)
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else if (Pipeline&&CurrentState==StateCPU)
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CPU_rd_dout <=Douta;
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CPU_rd_dout <=Douta;
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