//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Phy_sim.v ////
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//// Phy_sim.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2006/01/19 14:07:50 maverickist
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// Revision 1.2 2006/01/19 14:07:50 maverickist
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// verification is complete.
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// verification is complete.
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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// no message
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//
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//
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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module Phy_sim (
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module Phy_sim (
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input Gtx_clk ,//used only in GMII mode
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input Gtx_clk ,//used only in GMII mode
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output Rx_clk ,
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output Rx_clk ,
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output Tx_clk ,//used only in MII mode
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output Tx_clk ,//used only in MII mode
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input Tx_er ,
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input Tx_er ,
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input Tx_en ,
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input Tx_en ,
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input [7:0] Txd ,
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input [7:0] Txd ,
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output Rx_er ,
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output Rx_er ,
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output Rx_dv ,
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output Rx_dv ,
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output [7:0] Rxd ,
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output [7:0] Rxd ,
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output Crs ,
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output Crs ,
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output Col ,
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output Col ,
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input [2:0] Speed
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input [2:0] Speed
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);
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);
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// this file used to simulate Phy.
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// this file used to simulate Phy.
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// generate clk and loop the Tx data to Rx data
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// generate clk and loop the Tx data to Rx data
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// full duplex mode can be verified on loop mode.
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// full duplex mode can be verified on loop mode.
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// internal signals
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// internal signals
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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reg Clk_25m ;//used for 100 Mbps mode
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reg Clk_25m ;//used for 100 Mbps mode
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reg Clk_2_5m ;//used for 10 Mbps mode
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reg Clk_2_5m ;//used for 10 Mbps mode
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//wire Rx_clk ;
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//wire Rx_clk ;
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//wire Tx_clk ;//used only in MII mode
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//wire Tx_clk ;//used only in MII mode
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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always
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always
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begin
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begin
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#20 Clk_25m=0;
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#20 Clk_25m=0;
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#20 Clk_25m=1;
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#20 Clk_25m=1;
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end
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end
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always
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always
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begin
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begin
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#200 Clk_2_5m=0;
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#200 Clk_2_5m=0;
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#200 Clk_2_5m=1;
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#200 Clk_2_5m=1;
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end
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end
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assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
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assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
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assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
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assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
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assign Rx_dv =Tx_en ;
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assign Rx_dv =Tx_en ;
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assign Rxd =Txd ;
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assign Rxd =Txd ;
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assign Rx_er =0 ;
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assign Rx_er =0 ;
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assign Crs =Tx_en ;
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assign Crs =Tx_en ;
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assign Col =0 ;
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assign Col =0 ;
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