module host_sim (
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module host_sim (
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input Reset ,
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input Reset ,
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input Clk_reg ,
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input Clk_reg ,
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output reg CSB ,
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output reg CSB ,
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output reg WRB ,
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output reg WRB ,
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output reg CPU_init_end ,
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output reg CPU_init_end ,
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output reg [15:0] CD_in ,
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output reg [15:0] CD_in ,
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input [15:0] CD_out ,
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input [15:0] CD_out ,
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output reg [7:0] CA
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output reg [7:0] CA
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);
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);
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////////////////////////////////////////
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////////////////////////////////////////
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task CPU_init;
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task CPU_init;
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begin
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begin
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CA =0;
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CA =0;
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CD_in =0;
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CD_in =0;
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WRB =1;
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WRB =1;
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CSB =1;
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CSB =1;
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end
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end
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endtask
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endtask
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////////////////////////////////////////
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////////////////////////////////////////
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task CPU_wr;
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task CPU_wr;
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input[6:0] Addr;
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input[6:0] Addr;
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input[15:0] Data;
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input[15:0] Data;
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begin
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begin
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CA ={Addr,1'b0};
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CA ={Addr,1'b0};
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CD_in =Data;
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CD_in =Data;
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WRB =0;
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WRB =0;
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CSB =0;
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CSB =0;
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#20;
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#20;
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CA =0;
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CA =0;
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CD_in =0;
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CD_in =0;
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WRB =1;
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WRB =1;
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CSB =1;
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CSB =1;
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#20;
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#20;
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end
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end
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endtask
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endtask
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/////////////////////////////////////////
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/////////////////////////////////////////
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task CPU_rd;
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task CPU_rd;
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input[6:0] Addr;
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input[6:0] Addr;
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begin
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begin
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CA ={Addr,1'b0};
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CA ={Addr,1'b0};
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WRB =1;
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WRB =1;
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CSB =0;
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CSB =0;
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#20;
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#20;
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CA =0;
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CA =0;
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WRB =1;
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WRB =1;
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CSB =1;
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CSB =1;
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#20;
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#20;
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end
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end
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endtask
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endtask
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/////////////////////////////////////////
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/////////////////////////////////////////
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integer i;
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integer i;
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reg [31:0] CPU_data [255:0];
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reg [31:0] CPU_data [255:0];
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reg [7:0] write_times;
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reg [7:0] write_times;
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reg [7:0] write_add;
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reg [7:0] write_add;
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reg [15:0] write_data;
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reg [15:0] write_data;
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initial
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initial
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begin
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begin
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end
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end
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initial
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initial
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begin
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begin
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CPU_init;
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CPU_init;
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CPU_init_end=0;
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CPU_init_end=0;
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$readmemh("../data/CPU.vec",CPU_data);
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$readmemh("../data/CPU.vec",CPU_data);
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{write_times,write_add,write_data}=CPU_data[0];
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{write_times,write_add,write_data}=CPU_data[0];
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#90 ;
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#90 ;
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for (i=0;i<write_times;i=i+1)
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for (i=0;i<write_times;i=i+1)
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begin
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begin
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{write_times,write_add,write_data}=CPU_data[i];
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{write_times,write_add,write_data}=CPU_data[i];
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CPU_wr(write_add[6:0],write_data);
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CPU_wr(write_add[6:0],write_data);
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end
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end
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CPU_init_end=1;
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CPU_init_end=1;
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end
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end
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