//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// reg_int_sim.v ////
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//// reg_int_sim.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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module reg_int_sim (
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module reg_int_sim (
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input Reset ,
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input Reset ,
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input Clk_reg ,
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input Clk_reg ,
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//Tx host interface
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//Tx host interface
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output [4:0] Tx_Hwmark ,
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output [4:0] Tx_Hwmark ,
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output [4:0] Tx_Lwmark ,
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output [4:0] Tx_Lwmark ,
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output pause_frame_send_en ,
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output pause_frame_send_en ,
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output [15:0] pause_quanta_set ,
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output [15:0] pause_quanta_set ,
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output MAC_tx_add_en ,
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output MAC_tx_add_en ,
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output FullDuplex ,
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output FullDuplex ,
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output [3:0] MaxRetry ,
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output [3:0] MaxRetry ,
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output [5:0] IFGset ,
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output [5:0] IFGset ,
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output [7:0] MAC_tx_add_prom_data ,
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output [7:0] MAC_tx_add_prom_data ,
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output [2:0] MAC_tx_add_prom_add ,
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output [2:0] MAC_tx_add_prom_add ,
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output MAC_tx_add_prom_wr ,
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output MAC_tx_add_prom_wr ,
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output tx_pause_en ,
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output tx_pause_en ,
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output xoff_cpu ,
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output xoff_cpu ,
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output xon_cpu ,
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output xon_cpu ,
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//Rx host interface
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//Rx host interface
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output MAC_rx_add_chk_en ,
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output MAC_rx_add_chk_en ,
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output [7:0] MAC_rx_add_prom_data ,
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output [7:0] MAC_rx_add_prom_data ,
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output [2:0] MAC_rx_add_prom_add ,
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output [2:0] MAC_rx_add_prom_add ,
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output MAC_rx_add_prom_wr ,
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output MAC_rx_add_prom_wr ,
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output broadcast_filter_en ,
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output broadcast_filter_en ,
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output [15:0] broadcast_MAX ,
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output [15:0] broadcast_MAX ,
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output RX_APPEND_CRC ,
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output RX_APPEND_CRC ,
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output CRC_chk_en ,
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output CRC_chk_en ,
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output [5:0] RX_IFG_SET ,
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output [5:0] RX_IFG_SET ,
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output [15:0] RX_MAX_LENGTH ,// 1518
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output [15:0] RX_MAX_LENGTH ,// 1518
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output [6:0] RX_MIN_LENGTH ,// 64
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output [6:0] RX_MIN_LENGTH ,// 64
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//RMON host interface
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//RMON host interface
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output [5:0] CPU_rd_addr ,
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output [5:0] CPU_rd_addr ,
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output CPU_rd_apply ,
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output CPU_rd_apply ,
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input CPU_rd_grant ,
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input CPU_rd_grant ,
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input [31:0] CPU_rd_dout ,
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input [31:0] CPU_rd_dout ,
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//Phy int host interface
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//Phy int host interface
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output Line_loop_en ,
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output Line_loop_en ,
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output [2:0] Speed ,
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output [2:0] Speed ,
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//MII to CPU
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//MII to CPU
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output [7:0] Divider ,// Divider for the host clock
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output [7:0] Divider ,// Divider for the host clock
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output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
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output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
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output [4:0] Rgad ,// Register Address (within the PHY)
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output [4:0] Rgad ,// Register Address (within the PHY)
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output [4:0] Fiad ,// PHY Address
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output [4:0] Fiad ,// PHY Address
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output NoPre ,// No Preamble (no 32-bit preamble)
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output NoPre ,// No Preamble (no 32-bit preamble)
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output WCtrlData ,// Write Control Data operation
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output WCtrlData ,// Write Control Data operation
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output RStat ,// Read Status operation
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output RStat ,// Read Status operation
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output ScanStat ,// Scan Status operation
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output ScanStat ,// Scan Status operation
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input Busy ,// Busy Signal
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input Busy ,// Busy Signal
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input LinkFail ,// Link Integrity Signal
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input LinkFail ,// Link Integrity Signal
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input Nvalid ,// Invalid Status (qualifier for the valid scan result)
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input Nvalid ,// Invalid Status (qualifier for the valid scan result)
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input [15:0] Prsd ,// Read Status Data (data read from the PHY)
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input [15:0] Prsd ,// Read Status Data (data read from the PHY)
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input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
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input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
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);
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);
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assign Tx_Hwmark =5'h1e;
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assign Tx_Hwmark =5'h1e;
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assign Tx_Lwmark =5'h19;
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assign Tx_Lwmark =5'h19;
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assign pause_frame_send_en =0;
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assign pause_frame_send_en =0;
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assign pause_quanta_set =0;
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assign pause_quanta_set =0;
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assign MAC_tx_add_en =0;
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assign MAC_tx_add_en =0;
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assign FullDuplex =1;
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assign FullDuplex =1;
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assign MaxRetry =2;
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assign MaxRetry =2;
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assign IFGset =10;
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assign IFGset =10;
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assign MAC_tx_add_prom_data =0;
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assign MAC_tx_add_prom_data =0;
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assign MAC_tx_add_prom_add =0;
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assign MAC_tx_add_prom_add =0;
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assign MAC_tx_add_prom_wr =0;
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assign MAC_tx_add_prom_wr =0;
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assign tx_pause_en =0;
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assign tx_pause_en =0;
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assign xoff_cpu =0;
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assign xoff_cpu =0;
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assign xon_cpu =0;
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assign xon_cpu =0;
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assign MAC_rx_add_chk_en =0;
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assign MAC_rx_add_chk_en =0;
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assign MAC_rx_add_prom_data =0;
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assign MAC_rx_add_prom_data =0;
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assign MAC_rx_add_prom_add =0;
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assign MAC_rx_add_prom_add =0;
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assign MAC_rx_add_prom_wr =0;
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assign MAC_rx_add_prom_wr =0;
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assign broadcast_filter_en =0;
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assign broadcast_filter_en =0;
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assign broadcast_MAX =10;
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assign broadcast_MAX =10;
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assign RX_APPEND_CRC =0;
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assign RX_APPEND_CRC =0;
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assign CRC_chk_en =1;
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assign CRC_chk_en =1;
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assign RX_IFG_SET =10;
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assign RX_IFG_SET =10;
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assign RX_MAX_LENGTH =1518;
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assign RX_MAX_LENGTH =1518;
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assign RX_MIN_LENGTH =64;
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assign RX_MIN_LENGTH =64;
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assign CPU_rd_addr =0;
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assign CPU_rd_addr =0;
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assign CPU_rd_apply =0;
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assign CPU_rd_apply =0;
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assign Line_loop_en =0;
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assign Line_loop_en =0;
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assign Speed =3'b001;
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assign Speed =3'b001;
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