//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MAC_rx_FF.v ////
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//// MAC_rx_FF.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2008/08/17 11:41:30 maverickist
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// Revision 1.5 2006/06/25 04:58:56 maverickist
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// Revision 1.3 2006/01/19 14:07:54 maverickist
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// Revision 1.3 2006/01/19 14:07:54 maverickist
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// verification is complete.
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// verification is complete.
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//
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//
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// Revision 1.3 2005/12/16 06:44:16 Administrator
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// Revision 1.3 2005/12/16 06:44:16 Administrator
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// replaced tab with space.
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// replaced tab with space.
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// passed 9.6k length frame test.
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// passed 9.6k length frame test.
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//
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//
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// Revision 1.2 2005/12/13 12:15:37 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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// no message
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//
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//
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module MAC_rx_FF (
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module MAC_rx_FF (
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Reset ,
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Reset ,
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Clk_MAC ,
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Clk_MAC ,
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Clk_SYS ,
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Clk_SYS ,
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//MAC_rx_ctrl interface
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//MAC_rx_ctrl interface
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Fifo_data ,
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Fifo_data ,
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Fifo_data_en ,
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Fifo_data_en ,
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Fifo_full ,
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Fifo_full ,
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Fifo_data_err ,
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Fifo_data_err ,
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Fifo_data_end ,
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Fifo_data_end ,
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//CPU
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//CPU
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Rx_Hwmark,
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Rx_Hwmark,
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Rx_Lwmark,
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Rx_Lwmark,
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RX_APPEND_CRC,
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RX_APPEND_CRC,
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//user interface
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//user interface
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Rx_mac_ra ,
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Rx_mac_ra ,
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Rx_mac_rd ,
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Rx_mac_rd ,
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Rx_mac_data ,
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Rx_mac_data ,
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Rx_mac_BE ,
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Rx_mac_BE ,
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Rx_mac_sop ,
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Rx_mac_sop ,
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Rx_mac_pa,
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Rx_mac_pa,
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Rx_mac_eop
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Rx_mac_eop
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);
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);
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input Reset ;
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input Reset ;
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input Clk_MAC ;
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input Clk_MAC ;
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input Clk_SYS ;
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input Clk_SYS ;
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//MAC_rx_ctrl interface
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//MAC_rx_ctrl interface
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input [7:0] Fifo_data ;
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input [7:0] Fifo_data ;
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input Fifo_data_en ;
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input Fifo_data_en ;
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output Fifo_full ;
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output Fifo_full ;
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input Fifo_data_err ;
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input Fifo_data_err ;
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input Fifo_data_end ;
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input Fifo_data_end ;
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//CPU
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//CPU
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input RX_APPEND_CRC ;
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input RX_APPEND_CRC ;
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input [4:0] Rx_Hwmark ;
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input [4:0] Rx_Hwmark ;
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input [4:0] Rx_Lwmark ;
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input [4:0] Rx_Lwmark ;
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//user interface
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//user interface
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output Rx_mac_ra ;//
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output Rx_mac_ra ;//
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input Rx_mac_rd ;
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input Rx_mac_rd ;
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output [31:0] Rx_mac_data ;
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output [31:0] Rx_mac_data ;
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output [1:0] Rx_mac_BE ;
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output [1:0] Rx_mac_BE ;
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output Rx_mac_pa ;
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output Rx_mac_pa ;
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output Rx_mac_sop ;
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output Rx_mac_sop ;
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output Rx_mac_eop ;
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output Rx_mac_eop ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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parameter State_byte3 =4'd0;
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parameter State_byte3 =4'd0;
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parameter State_byte2 =4'd1;
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parameter State_byte2 =4'd1;
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parameter State_byte1 =4'd2;
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parameter State_byte1 =4'd2;
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parameter State_byte0 =4'd3;
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parameter State_byte0 =4'd3;
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parameter State_be0 =4'd4;
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parameter State_be0 =4'd4;
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parameter State_be3 =4'd5;
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parameter State_be3 =4'd5;
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parameter State_be2 =4'd6;
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parameter State_be2 =4'd6;
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parameter State_be1 =4'd7;
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parameter State_be1 =4'd7;
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parameter State_err_end =4'd8;
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parameter State_err_end =4'd8;
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parameter State_idle =4'd9;
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parameter State_idle =4'd9;
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parameter SYS_read =3'd0;
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parameter SYS_read =3'd0;
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parameter SYS_pause =3'd1;
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parameter SYS_pause =3'd1;
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parameter SYS_wait_end =3'd2;
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parameter SYS_wait_end =3'd2;
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parameter SYS_idle =3'd3;
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parameter SYS_idle =3'd3;
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parameter FF_emtpy_err =3'd4;
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parameter FF_emtpy_err =3'd4;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
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reg [35:0] Din;
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reg [35:0] Din;
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reg [35:0] Din_tmp;
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reg [35:0] Din_tmp;
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reg [35:0] Din_tmp_reg;
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reg [35:0] Din_tmp_reg;
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wire[35:0] Dout;
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wire[35:0] Dout;
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reg Wr_en;
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reg Wr_en;
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reg Wr_en_tmp;
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reg Wr_en_tmp;
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reg Wr_en_ptr;
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reg Wr_en_ptr;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
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reg Full;
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reg Full;
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reg Almost_full;
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reg Almost_full;
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reg Empty /* synthesis syn_keep=1 */;
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reg Empty /* synthesis syn_keep=1 */;
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reg [3:0] Current_state /* synthesis syn_keep=1 */;
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reg [3:0] Current_state /* synthesis syn_keep=1 */;
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reg [3:0] Next_state;
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reg [3:0] Next_state;
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reg [7:0] Fifo_data_byte0;
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reg [7:0] Fifo_data_byte0;
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reg [7:0] Fifo_data_byte1;
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reg [7:0] Fifo_data_byte1;
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reg [7:0] Fifo_data_byte2;
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reg [7:0] Fifo_data_byte2;
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reg [7:0] Fifo_data_byte3;
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reg [7:0] Fifo_data_byte3;
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reg Fifo_data_en_dl1;
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reg Fifo_data_en_dl1;
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reg [7:0] Fifo_data_dl1;
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reg [7:0] Fifo_data_dl1;
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reg Rx_mac_sop_tmp ;
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reg Rx_mac_sop_tmp ;
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reg Rx_mac_sop ;
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reg Rx_mac_sop ;
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reg Rx_mac_ra ;
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reg Rx_mac_ra ;
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reg Rx_mac_pa ;
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reg Rx_mac_pa ;
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reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
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reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
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reg [2:0] Next_state_SYS ;
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reg [2:0] Next_state_SYS ;
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reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
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reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
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reg Packet_number_sub ;
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reg Packet_number_sub ;
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wire Packet_number_add_edge;
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wire Packet_number_add_edge;
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reg Packet_number_add_dl1;
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reg Packet_number_add_dl1;
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reg Packet_number_add_dl2;
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reg Packet_number_add_dl2;
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reg Packet_number_add ;
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reg Packet_number_add ;
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reg Packet_number_add_tmp ;
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reg Packet_number_add_tmp ;
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reg Packet_number_add_tmp_dl1;
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reg Packet_number_add_tmp_dl1;
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reg Packet_number_add_tmp_dl2;
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reg Packet_number_add_tmp_dl2;
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reg Rx_mac_sop_tmp_dl1;
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reg Rx_mac_sop_tmp_dl1;
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reg [35:0] Dout_dl1;
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reg [35:0] Dout_dl1;
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reg [4:0] Fifo_data_count;
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reg [4:0] Fifo_data_count;
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reg Rx_mac_pa_tmp ;
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reg Rx_mac_pa_tmp ;
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reg Add_wr_jump_tmp ;
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reg Add_wr_jump_tmp ;
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reg Add_wr_jump_tmp_pl1 ;
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reg Add_wr_jump_tmp_pl1 ;
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reg Add_wr_jump ;
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reg Add_wr_jump ;
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reg Add_wr_jump_rd_pl1 ;
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reg Add_wr_jump_rd_pl1 ;
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reg [4:0] Rx_Hwmark_pl ;
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reg [4:0] Rx_Hwmark_pl ;
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reg [4:0] Rx_Lwmark_pl ;
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reg [4:0] Rx_Lwmark_pl ;
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reg Addr_freshed_ptr ;
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reg Addr_freshed_ptr ;
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integer i ;
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integer i ;
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//******************************************************************************
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//******************************************************************************
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//domain Clk_MAC,write data to dprom.a-port for write
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//domain Clk_MAC,write data to dprom.a-port for write
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//******************************************************************************
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//******************************************************************************
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always @ (posedge Clk_MAC or posedge Reset)
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always @ (posedge Clk_MAC or posedge Reset)
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if (Reset)
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if (Reset)
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Current_state <=State_idle;
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Current_state <=State_idle;
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else
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else
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Current_state <=Next_state;
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Current_state <=Next_state;
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always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
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always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
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case (Current_state)
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case (Current_state)
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State_idle:
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State_idle:
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if (Fifo_data_en)
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if (Fifo_data_en)
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Next_state =State_byte3;
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Next_state =State_byte3;
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else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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State_byte3:
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State_byte3:
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if (Fifo_data_en)
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if (Fifo_data_en)
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Next_state =State_byte2;
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Next_state =State_byte2;
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else if (Fifo_data_err)
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else if (Fifo_data_err)
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Next_state =State_err_end;
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Next_state =State_err_end;
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else if (Fifo_data_end)
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else if (Fifo_data_end)
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Next_state =State_be1;
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Next_state =State_be1;
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else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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State_byte2:
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State_byte2:
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if (Fifo_data_en)
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if (Fifo_data_en)
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Next_state =State_byte1;
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Next_state =State_byte1;
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else if (Fifo_data_err)
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else if (Fifo_data_err)
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Next_state =State_err_end;
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Next_state =State_err_end;
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else if (Fifo_data_end)
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else if (Fifo_data_end)
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Next_state =State_be2;
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Next_state =State_be2;
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else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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State_byte1:
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State_byte1:
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if (Fifo_data_en)
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if (Fifo_data_en)
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Next_state =State_byte0;
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Next_state =State_byte0;
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else if (Fifo_data_err)
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else if (Fifo_data_err)
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Next_state =State_err_end;
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Next_state =State_err_end;
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else if (Fifo_data_end)
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else if (Fifo_data_end)
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Next_state =State_be3;
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Next_state =State_be3;
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else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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State_byte0:
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State_byte0:
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if (Fifo_data_en)
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if (Fifo_data_en)
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Next_state =State_byte3;
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Next_state =State_byte3;
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else if (Fifo_data_err)
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else if (Fifo_data_err)
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Next_state =State_err_end;
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Next_state =State_err_end;
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else if (Fifo_data_end)
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else if (Fifo_data_end)
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Next_state =State_be0;
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Next_state =State_be0;
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else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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State_be1:
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State_be1:
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Next_state =State_idle;
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Next_state =State_idle;
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State_be2:
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State_be2:
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Next_state =State_idle;
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Next_state =State_idle;
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State_be3:
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State_be3:
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Next_state =State_idle;
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Next_state =State_idle;
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State_be0:
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State_be0:
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Next_state =State_idle;
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Next_state =State_idle;
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State_err_end:
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State_err_end:
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Next_state =State_idle;
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Next_state =State_idle;
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default:
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default:
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Next_state =State_idle;
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Next_state =State_idle;
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endcase
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endcase
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//
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//
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always @ (posedge Clk_MAC or posedge Reset)
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always @ (posedge Clk_MAC or posedge Reset)
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if (Reset)
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if (Reset)
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Add_wr_reg <=0;
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Add_wr_reg <=0;
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else if (Current_state==State_idle)
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else if (Current_state==State_idle)
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Add_wr_reg <=Add_wr;
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Add_wr_reg <=Add_wr;
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|
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//
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//
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|
|
|
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always @ (posedge Reset or posedge Clk_MAC)
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always @ (posedge Reset or posedge Clk_MAC)
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if (Reset)
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if (Reset)
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Add_wr_gray <=0;
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Add_wr_gray <=0;
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else
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else
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begin
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begin
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Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
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Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
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for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
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for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
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Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
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Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
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end
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end
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|
|
//
|
//
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_rd_gray_dl1 <=0;
|
Add_rd_gray_dl1 <=0;
|
else
|
else
|
Add_rd_gray_dl1 <=Add_rd_gray;
|
Add_rd_gray_dl1 <=Add_rd_gray;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
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always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_rd_ungray =0;
|
Add_rd_ungray =0;
|
else
|
else
|
begin
|
begin
|
Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
|
Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
|
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
|
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
|
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
|
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
|
end
|
end
|
assign Add_wr_pluse=Add_wr+1;
|
assign Add_wr_pluse=Add_wr+1;
|
assign Add_wr_pluse4=Add_wr+4;
|
assign Add_wr_pluse4=Add_wr+4;
|
assign Add_wr_pluse3=Add_wr+3;
|
assign Add_wr_pluse3=Add_wr+3;
|
assign Add_wr_pluse2=Add_wr+2;
|
assign Add_wr_pluse2=Add_wr+2;
|
|
|
|
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Full <=0;
|
Full <=0;
|
else if (Add_wr_pluse==Add_rd_ungray)
|
else if (Add_wr_pluse==Add_rd_ungray)
|
Full <=1;
|
Full <=1;
|
else
|
else
|
Full <=0;
|
Full <=0;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Almost_full <=0;
|
Almost_full <=0;
|
else if (Add_wr_pluse4==Add_rd_ungray||
|
else if (Add_wr_pluse4==Add_rd_ungray||
|
Add_wr_pluse3==Add_rd_ungray||
|
Add_wr_pluse3==Add_rd_ungray||
|
Add_wr_pluse2==Add_rd_ungray||
|
Add_wr_pluse2==Add_rd_ungray||
|
Add_wr_pluse==Add_rd_ungray
|
Add_wr_pluse==Add_rd_ungray
|
)
|
)
|
Almost_full <=1;
|
Almost_full <=1;
|
else
|
else
|
Almost_full <=0;
|
Almost_full <=0;
|
|
|
assign Fifo_full =Almost_full;
|
assign Fifo_full =Almost_full;
|
|
|
//
|
//
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr <=0;
|
Add_wr <=0;
|
else if (Current_state==State_err_end)
|
else if (Current_state==State_err_end)
|
Add_wr <=Add_wr_reg;
|
Add_wr <=Add_wr_reg;
|
else if (Wr_en&&!Full)
|
else if (Wr_en&&!Full)
|
Add_wr <=Add_wr +1;
|
Add_wr <=Add_wr +1;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr_jump_tmp <=0;
|
Add_wr_jump_tmp <=0;
|
else if (Current_state==State_err_end)
|
else if (Current_state==State_err_end)
|
Add_wr_jump_tmp <=1;
|
Add_wr_jump_tmp <=1;
|
else
|
else
|
Add_wr_jump_tmp <=0;
|
Add_wr_jump_tmp <=0;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr_jump_tmp_pl1 <=0;
|
Add_wr_jump_tmp_pl1 <=0;
|
else
|
else
|
Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
|
Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr_jump <=0;
|
Add_wr_jump <=0;
|
else if (Current_state==State_err_end)
|
else if (Current_state==State_err_end)
|
Add_wr_jump <=1;
|
Add_wr_jump <=1;
|
else if (Add_wr_jump_tmp_pl1)
|
else if (Add_wr_jump_tmp_pl1)
|
Add_wr_jump <=0;
|
Add_wr_jump <=0;
|
|
|
//
|
//
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Fifo_data_en_dl1 <=0;
|
Fifo_data_en_dl1 <=0;
|
else
|
else
|
Fifo_data_en_dl1 <=Fifo_data_en;
|
Fifo_data_en_dl1 <=Fifo_data_en;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Fifo_data_dl1 <=0;
|
Fifo_data_dl1 <=0;
|
else
|
else
|
Fifo_data_dl1 <=Fifo_data;
|
Fifo_data_dl1 <=Fifo_data;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Fifo_data_byte3 <=0;
|
Fifo_data_byte3 <=0;
|
else if (Current_state==State_byte3&&Fifo_data_en_dl1)
|
else if (Current_state==State_byte3&&Fifo_data_en_dl1)
|
Fifo_data_byte3 <=Fifo_data_dl1;
|
Fifo_data_byte3 <=Fifo_data_dl1;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Fifo_data_byte2 <=0;
|
Fifo_data_byte2 <=0;
|
else if (Current_state==State_byte2&&Fifo_data_en_dl1)
|
else if (Current_state==State_byte2&&Fifo_data_en_dl1)
|
Fifo_data_byte2 <=Fifo_data_dl1;
|
Fifo_data_byte2 <=Fifo_data_dl1;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Fifo_data_byte1 <=0;
|
Fifo_data_byte1 <=0;
|
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
|
else if (Current_state==State_byte1&&Fifo_data_en_dl1)
|
Fifo_data_byte1 <=Fifo_data_dl1;
|
Fifo_data_byte1 <=Fifo_data_dl1;
|
|
|
always @ (* )
|
always @ (* )
|
case (Current_state)
|
case (Current_state)
|
State_be0:
|
State_be0:
|
Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
|
Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
|
State_be1:
|
State_be1:
|
Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
|
Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
|
State_be2:
|
State_be2:
|
Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
|
Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
|
State_be3:
|
State_be3:
|
Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
|
Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
|
default:
|
default:
|
Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
|
Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
|
endcase
|
endcase
|
|
|
always @ (*)
|
always @ (*)
|
if (Current_state==State_be0||Current_state==State_be1||
|
if (Current_state==State_be0||Current_state==State_be1||
|
Current_state==State_be2||Current_state==State_be3||
|
Current_state==State_be2||Current_state==State_be3||
|
(Current_state==State_byte0&&Fifo_data_en))
|
(Current_state==State_byte0&&Fifo_data_en))
|
Wr_en_tmp =1;
|
Wr_en_tmp =1;
|
else
|
else
|
Wr_en_tmp =0;
|
Wr_en_tmp =0;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Din_tmp_reg <=0;
|
Din_tmp_reg <=0;
|
else if(Wr_en_tmp)
|
else if(Wr_en_tmp)
|
Din_tmp_reg <=Din_tmp;
|
Din_tmp_reg <=Din_tmp;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Wr_en_ptr <=0;
|
Wr_en_ptr <=0;
|
else if(Current_state==State_idle)
|
else if(Current_state==State_idle)
|
Wr_en_ptr <=0;
|
Wr_en_ptr <=0;
|
else if(Wr_en_tmp)
|
else if(Wr_en_tmp)
|
Wr_en_ptr <=1;
|
Wr_en_ptr <=1;
|
|
|
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
|
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Wr_en <=0;
|
Wr_en <=0;
|
Din <=0;
|
Din <=0;
|
end
|
end
|
else if(RX_APPEND_CRC)
|
else if(RX_APPEND_CRC)
|
begin
|
begin
|
Wr_en <=Wr_en_tmp;
|
Wr_en <=Wr_en_tmp;
|
Din <=Din_tmp;
|
Din <=Din_tmp;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Wr_en <=Wr_en_tmp&&Wr_en_ptr;
|
Wr_en <=Wr_en_tmp&&Wr_en_ptr;
|
Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
|
Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
|
end
|
end
|
|
|
//this signal for read side to handle the packet number in fifo
|
//this signal for read side to handle the packet number in fifo
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Packet_number_add_tmp <=0;
|
Packet_number_add_tmp <=0;
|
else if (Current_state==State_be0||Current_state==State_be1||
|
else if (Current_state==State_be0||Current_state==State_be1||
|
Current_state==State_be2||Current_state==State_be3)
|
Current_state==State_be2||Current_state==State_be3)
|
Packet_number_add_tmp <=1;
|
Packet_number_add_tmp <=1;
|
else
|
else
|
Packet_number_add_tmp <=0;
|
Packet_number_add_tmp <=0;
|
|
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Packet_number_add_tmp_dl1 <=0;
|
Packet_number_add_tmp_dl1 <=0;
|
Packet_number_add_tmp_dl2 <=0;
|
Packet_number_add_tmp_dl2 <=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
|
Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
|
Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
|
Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
|
end
|
end
|
|
|
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
|
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
|
//expand to two cycles long almost=16 ns
|
//expand to two cycles long almost=16 ns
|
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
|
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
|
always @ (posedge Clk_MAC or posedge Reset)
|
always @ (posedge Clk_MAC or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Packet_number_add <=0;
|
Packet_number_add <=0;
|
else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
|
else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
|
Packet_number_add <=1;
|
Packet_number_add <=1;
|
else
|
else
|
Packet_number_add <=0;
|
Packet_number_add <=0;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//******************************************************************************
|
//******************************************************************************
|
//domain Clk_SYS,read data from dprom.b-port for read
|
//domain Clk_SYS,read data from dprom.b-port for read
|
//******************************************************************************
|
//******************************************************************************
|
|
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Current_state_SYS <=SYS_idle;
|
Current_state_SYS <=SYS_idle;
|
else
|
else
|
Current_state_SYS <=Next_state_SYS;
|
Current_state_SYS <=Next_state_SYS;
|
|
|
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
|
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
|
case (Current_state_SYS)
|
case (Current_state_SYS)
|
SYS_idle:
|
SYS_idle:
|
if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
|
if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
|
Next_state_SYS =SYS_read;
|
Next_state_SYS =SYS_read;
|
else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
|
else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
|
Next_state_SYS =FF_emtpy_err;
|
Next_state_SYS =FF_emtpy_err;
|
else
|
else
|
Next_state_SYS =Current_state_SYS;
|
Next_state_SYS =Current_state_SYS;
|
SYS_read:
|
SYS_read:
|
if (Dout[35])
|
if (Dout[35])
|
Next_state_SYS =SYS_wait_end;
|
Next_state_SYS =SYS_wait_end;
|
else if (!Rx_mac_rd)
|
else if (!Rx_mac_rd)
|
Next_state_SYS =SYS_pause;
|
Next_state_SYS =SYS_pause;
|
else if (Empty)
|
else if (Empty)
|
Next_state_SYS =FF_emtpy_err;
|
Next_state_SYS =FF_emtpy_err;
|
else
|
else
|
Next_state_SYS =Current_state_SYS;
|
Next_state_SYS =Current_state_SYS;
|
SYS_pause:
|
SYS_pause:
|
if (Rx_mac_rd)
|
if (Rx_mac_rd)
|
Next_state_SYS =SYS_read;
|
Next_state_SYS =SYS_read;
|
else
|
else
|
Next_state_SYS =Current_state_SYS;
|
Next_state_SYS =Current_state_SYS;
|
FF_emtpy_err:
|
FF_emtpy_err:
|
if (!Empty)
|
if (!Empty)
|
Next_state_SYS =SYS_read;
|
Next_state_SYS =SYS_read;
|
else
|
else
|
Next_state_SYS =Current_state_SYS;
|
Next_state_SYS =Current_state_SYS;
|
SYS_wait_end:
|
SYS_wait_end:
|
if (!Rx_mac_rd)
|
if (!Rx_mac_rd)
|
Next_state_SYS =SYS_idle;
|
Next_state_SYS =SYS_idle;
|
else
|
else
|
Next_state_SYS =Current_state_SYS;
|
Next_state_SYS =Current_state_SYS;
|
default:
|
default:
|
Next_state_SYS =SYS_idle;
|
Next_state_SYS =SYS_idle;
|
endcase
|
endcase
|
|
|
|
|
//gen Rx_mac_ra
|
//gen Rx_mac_ra
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Packet_number_add_dl1 <=0;
|
Packet_number_add_dl1 <=0;
|
Packet_number_add_dl2 <=0;
|
Packet_number_add_dl2 <=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Packet_number_add_dl1 <=Packet_number_add;
|
Packet_number_add_dl1 <=Packet_number_add;
|
Packet_number_add_dl2 <=Packet_number_add_dl1;
|
Packet_number_add_dl2 <=Packet_number_add_dl1;
|
end
|
end
|
assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
|
assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
|
|
|
always @ (Current_state_SYS or Next_state_SYS)
|
always @ (Current_state_SYS or Next_state_SYS)
|
if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
|
if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
|
Packet_number_sub =1;
|
Packet_number_sub =1;
|
else
|
else
|
Packet_number_sub =0;
|
Packet_number_sub =0;
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Packet_number_inFF <=0;
|
Packet_number_inFF <=0;
|
else if (Packet_number_add_edge&&!Packet_number_sub)
|
else if (Packet_number_add_edge&&!Packet_number_sub)
|
Packet_number_inFF <=Packet_number_inFF + 1;
|
Packet_number_inFF <=Packet_number_inFF + 1;
|
else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
|
else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
|
Packet_number_inFF <=Packet_number_inFF - 1;
|
Packet_number_inFF <=Packet_number_inFF - 1;
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Fifo_data_count <=0;
|
Fifo_data_count <=0;
|
else
|
else
|
Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
|
Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Rx_Hwmark_pl <=0;
|
Rx_Hwmark_pl <=0;
|
Rx_Lwmark_pl <=0;
|
Rx_Lwmark_pl <=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Rx_Hwmark_pl <=Rx_Hwmark;
|
Rx_Hwmark_pl <=Rx_Hwmark;
|
Rx_Lwmark_pl <=Rx_Lwmark;
|
Rx_Lwmark_pl <=Rx_Lwmark;
|
end
|
end
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Rx_mac_ra <=0;
|
Rx_mac_ra <=0;
|
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
|
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
|
Rx_mac_ra <=0;
|
Rx_mac_ra <=0;
|
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
|
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
|
Rx_mac_ra <=1;
|
Rx_mac_ra <=1;
|
|
|
|
|
//control Add_rd signal;
|
//control Add_rd signal;
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_rd <=0;
|
Add_rd <=0;
|
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
|
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
|
Add_rd <=Add_rd + 1;
|
Add_rd <=Add_rd + 1;
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_rd_pl1 <=0;
|
Add_rd_pl1 <=0;
|
else
|
else
|
Add_rd_pl1 <=Add_rd;
|
Add_rd_pl1 <=Add_rd;
|
|
|
always @ (*)
|
always @ (*)
|
if (Add_rd_pl1==Add_rd)
|
if (Add_rd_pl1==Add_rd)
|
Addr_freshed_ptr =0;
|
Addr_freshed_ptr =0;
|
else
|
else
|
Addr_freshed_ptr =1;
|
Addr_freshed_ptr =1;
|
|
|
//
|
//
|
always @ (posedge Reset or posedge Clk_SYS)
|
always @ (posedge Reset or posedge Clk_SYS)
|
if (Reset)
|
if (Reset)
|
Add_rd_gray <=0;
|
Add_rd_gray <=0;
|
else
|
else
|
begin
|
begin
|
Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
|
Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
|
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
|
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
|
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
|
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
|
end
|
end
|
//
|
//
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr_gray_dl1 <=0;
|
Add_wr_gray_dl1 <=0;
|
else
|
else
|
Add_wr_gray_dl1 <=Add_wr_gray;
|
Add_wr_gray_dl1 <=Add_wr_gray;
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr_jump_rd_pl1 <=0;
|
Add_wr_jump_rd_pl1 <=0;
|
else
|
else
|
Add_wr_jump_rd_pl1 <=Add_wr_jump;
|
Add_wr_jump_rd_pl1 <=Add_wr_jump;
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Add_wr_ungray =0;
|
Add_wr_ungray =0;
|
else if (!Add_wr_jump_rd_pl1)
|
else if (!Add_wr_jump_rd_pl1)
|
begin
|
begin
|
Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
|
Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
|
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
|
for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
|
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
|
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
|
end
|
end
|
//empty signal gen
|
//empty signal gen
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Empty <=1;
|
Empty <=1;
|
else if (Add_rd==Add_wr_ungray)
|
else if (Add_rd==Add_wr_ungray)
|
Empty <=1;
|
Empty <=1;
|
else
|
else
|
Empty <=0;
|
Empty <=0;
|
|
|
|
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Dout_dl1 <=0;
|
Dout_dl1 <=0;
|
else
|
else
|
Dout_dl1 <=Dout;
|
Dout_dl1 <=Dout;
|
|
|
assign Rx_mac_data =Dout_dl1[31:0];
|
assign Rx_mac_data =Dout_dl1[31:0];
|
assign Rx_mac_BE =Dout_dl1[33:32];
|
assign Rx_mac_BE =Dout_dl1[33:32];
|
assign Rx_mac_eop =Dout_dl1[35];
|
assign Rx_mac_eop =Dout_dl1[35];
|
|
|
//aligned to Addr_rd
|
//aligned to Addr_rd
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Rx_mac_pa_tmp <=0;
|
Rx_mac_pa_tmp <=0;
|
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
|
else if (Current_state_SYS==SYS_read&&!(Dout[35]&&Addr_freshed_ptr))
|
Rx_mac_pa_tmp <=1;
|
Rx_mac_pa_tmp <=1;
|
else
|
else
|
Rx_mac_pa_tmp <=0;
|
Rx_mac_pa_tmp <=0;
|
|
|
|
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Rx_mac_pa <=0;
|
Rx_mac_pa <=0;
|
else
|
else
|
Rx_mac_pa <=Rx_mac_pa_tmp;
|
Rx_mac_pa <=Rx_mac_pa_tmp;
|
|
|
|
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
Rx_mac_sop_tmp <=0;
|
Rx_mac_sop_tmp <=0;
|
else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
|
else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
|
Rx_mac_sop_tmp <=1;
|
Rx_mac_sop_tmp <=1;
|
else
|
else
|
Rx_mac_sop_tmp <=0;
|
Rx_mac_sop_tmp <=0;
|
|
|
|
|
|
|
always @ (posedge Clk_SYS or posedge Reset)
|
always @ (posedge Clk_SYS or posedge Reset)
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Rx_mac_sop_tmp_dl1 <=0;
|
Rx_mac_sop_tmp_dl1 <=0;
|
Rx_mac_sop <=0;
|
Rx_mac_sop <=0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
|
Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
|
Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
|
Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
|
end
|
end
|
|
|
|
|
|
|
//******************************************************************************
|
//******************************************************************************
|
|
|
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
|
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
|
.data_a (Din ),
|
.data_a (Din ),
|
.wren_a (Wr_en ),
|
.wren_a (Wr_en ),
|
.address_a (Add_wr ),
|
.address_a (Add_wr ),
|
.address_b (Add_rd ),
|
.address_b (Add_rd ),
|
.clock_a (Clk_MAC ),
|
.clock_a (Clk_MAC ),
|
.clock_b (Clk_SYS ),
|
.clock_b (Clk_SYS ),
|
.q_b (Dout ));
|
.q_b (Dout ));
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
|